Redistribution layer metallic structure and method

1 . A method of fabricating an integrated circuit (IC) structure, comprising:

forming first IC devices on a first frontside of a first semiconductor substrate and second IC devices on a second frontside of a second semiconductor substrate;

forming a first contact pad over the first IC devices from the first frontside of the first semiconductor substrate and a second contact pad over the second IC device from the second frontside of the second semiconductor substrate;

bonding the first contact pad to the second contact pad such that the first and second IC devices are electrically connected; and

forming a conductive structure on a first backside of the first semiconductor substrate, wherein the conductive structure includes a through via (TV), a backside metal (BSM) feature, and a backside redistribution layer (BRDL), and wherein

the TV is extending through the first semiconductor substrate and electrically connected the first and second IC devices to the BRDL, and

the BSM feature is extended into a portion of the first semiconductor substrate and electrically connected to the TV.

2 . The method of claim 1 , further comprising

forming a shallow trench isolation (STI) feature on the first frontside of the first semiconductor substrate and defining active regions; and

forming a first interconnect structure over the first IC devices and coupling the first IC devices into a first circuit, wherein the first interconnect structure includes a first metal line, and the first hybrid bonding layer are electrically connected to the first IC devices through the first interconnect structure.

3 . The method of claim 2 , wherein the forming a conductive structure further includes

patterning the first semiconductor substrate from the first backside to form a through hole in the first semiconductor substrate such that the first metal line is exposed in the through hole;

patterning the first semiconductor substrate from the first backside to form a BSM trench;

filling the through hole and the BSM trench with a conductive material to form the TV and the BSM feature, respectively; and

forming the BRDL over the TV and the BSM feature, the BRDL being embedded in a passivation layer.

4 . The method of claim 3 , wherein the patterning the first semiconductor substrate from the first backside to form a through hole in the first semiconductor substrate includes patterning the first semiconductor substrate to form the through hole penetrating through the STI feature.

5 . The method of claim 4 , wherein the patterning the first semiconductor substrate from the first backside to form a through hole in the first semiconductor substrate includes

performing a first patterning process to form a first trench in the first semiconductor substrate;

performing a second patterning process to deepen the first trench such that the STI feature is exposed in the deepened first trench; and

performing a third patterning process to further etch through the STI feature in the first deepened trench to form the through hole such that the first metal line is exposed in the through hole.

6 . The method of claim 5 , wherein the performing a second patterning process to deepen the first trench also simultaneously form the BSM trench in the first semiconductor substrate.

7 . The method of claim 6 , wherein

the first interconnect structure is embedded in an interlayer dielectric (ILD) layer; and

the performing a third patterning process includes etch the ILD layer such that the first metal line is exposed.

8 . The method of claim 6 , wherein the filling the through hole and the BSM trench with a conductive material to form the TV and the BSM feature further includes applying a chemical mechanical polishing process to the conductive material to remove excessive portions of the conductive material.

9 . The method of claim 4 , wherein the patterning the first semiconductor substrate from the first backside to form a through hole in the first semiconductor substrate includes

performing a first patterning process to form a TV trench and a BSM trench in the first semiconductor substrate; and

performing a second patterning process to further etch through the STI feature in the TV trench to form the through hole such that the first metal line is exposed in the through hole.

10 . The method of claim 4 , wherein

the patterning the first semiconductor substrate from the first backside to form a through hole in the first semiconductor substrate includes performing a first patterning process to form the through hole such that the first metal line is exposed in the through hole; and

performing a second patterning process to form a TV trench in the first semiconductor substrate.

11 . The method of claim 1 , wherein the forming a conductive structure includes forming the BSM feature designed as an inductor.

12 . A method of fabricating an integrated circuit (IC) structure, comprising:

forming first IC devices on a first frontside of a first substrate;

forming an interconnect structure having a first metal line over the first IC devices;

bonding the first substrate and a second substrate such that the first frontside of the first substrate and a second frontside of the second substrate are facing each other, the interconnect structure electrically coupling the first IC devices into an integrated circuit;

performing a first patterning process from a first backside of the first substrate to form a first trench in the first substrate;

performing a second patterning process to form a second trench in the first substrate and deepen the first trench such that a shallow trench isolation (STI) feature is exposed in the first trench;

performing a third patterning process to further etch through the STI feature in the first trench to form a through hole such that the first metal line is exposed in the through hole; and

filling the through hole and the second trench with a conductive material to form a through via (TV) and a backside metal (BSM) feature, respectively.

13 . The method of claim 12 , further comprising forming a backside redistribution layer (BRDL) and a bond pad over the TV and the BSM feature, the BRDL being embedded in a passivation layer.

14 . The method of claim 13 , wherein the bond pad is electrically connected to the TV through the BRDL and the BSM feature.

15 . The method of claim 14 , wherein the BSM feature includes a first portion designed as an inductor and a second portion designed as a thermal dissipation structure.

16 . The method of claim 12 , wherein

the interconnect structure is embedded in an interlayer dielectric (ILD) layer;

the performing a third patterning process includes etch the ILD layer such that the first metal line is exposed; and

the filling the through hole and the second trench with a conductive material to form a TV and a BSM feature further includes applying a chemical mechanical polishing process to the conductive material to remove excessive portions of the conductive material.

17 . A method of fabricating an integrated circuit (IC) structure, comprising:

forming first IC devices on a first frontside of a first substrate;

forming an interconnect structure having a first metal line over the first IC devices;

bonding the first substrate and a second substrate such that the first frontside of the first substrate and a second frontside of the second substrate are facing each other, the interconnect structure electrically coupling the first IC devices into an integrated circuit;

performing a first patterning process from a first backside of the first substrate to form a first trench in the first substrate;

performing a second patterning process to form a second trench in the first substrate and deepen the first trench such that a shallow trench isolation (STI) feature is exposed in the first trench;

performing a third patterning process to further etch through the STI feature in the first trench to form a through hole such that the first metal line is exposed in the through hole;

filling the through hole and the second trench with a conductive material to form a through via (TV) and a backside metal (BSM) feature, respectively; and

forming a backside redistribution layer (BRDL) and a bond pad over the TV and the BSM feature.

18 . The method of claim 17 , wherein

the bond pad is electrically connected to the TV through the BRDL and the BSM feature; and

the BSM feature includes a first portion designed as an inductor and a second portion designed as a thermal dissipation structure.

19 . The method of claim 17 , wherein

the interconnect structure is embedded in an interlayer dielectric (ILD) layer; and

the BRDL being embedded in a passivation layer.

20 . The method of claim 19 , wherein

the performing a third patterning process includes etching the ILD layer such that the first metal line is exposed; and

the filling the through hole and the second trench with a conductive material to form a TV and a BSM feature further includes applying a chemical mechanical polishing process to the conductive material to remove excessive portions of the conductive material.