IP Library Granted Patent US 12685101
Granted Patent B2
US 12685101 · App. 18/077,382 · Granted Jul 14, 2026

Semiconductor device with a liner layer

Inventor: Tse-Yao Huang (Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L21/76846H01L21/76831H01L21/76877H01L23/5226
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Quick Facts
Patent No.
US 12685101
App. No.
18/077,382
Granted
Jul 14, 2026
Kind
B2
Abstract

The present application discloses a semiconductor device. The semiconductor device includes a substrate; a first dielectric layer positioned on the substrate; a first opening positioned along the first dielectric layer to expose the substrate; a first liner layer conformally positioned in the first opening and on a top surface of the first dielectric layer; an energy-removable layer positioned in the first opening; a second dielectric layer positioned on the first liner layer; and a second opening positioned along the second dielectric layer to expose the energy-removable layer. The second dielectric layer has etching selectivity to the first liner layer.

Claims (28)

1 . A semiconductor device, comprising:

a substrate;

a first dielectric layer positioned on the substrate, wherein the first dielectric layer has a first opening;

a second dielectric layer positioned on the first dielectric layer, wherein the second dielectric layer has a second opening;

a conductive structure comprising:

a bottom portion positioned along the first dielectric layer within the first opening thereof and on the substrate; and

a top portion positioned along the second dielectric layer within the second opening thereof and on the bottom portion; and

a first liner layer positioned between the bottom portion and the first dielectric layer, between the bottom portion and the substrate, and between the second dielectric layer and the first dielectric layer;

wherein the second dielectric layer has etching selectivity to the first liner layer;

wherein the first liner layer comprises titanium nitride, tantalum nitride, or a combination thereof.

2 . The semiconductor device of claim 1 , wherein a width of the bottom portion of the conductive structure is less than a width of the top portion thereof, wherein a top surface of the top portion of the conductive structure is coplanar with a top surface of the second dielectric layer.

3 . The semiconductor device of claim 2 , wherein the first dielectric layer and the second dielectric layer comprise a same material.

4 . The semiconductor device of claim 2 , wherein the first dielectric layer and the second dielectric layer comprise different materials.

5 . The semiconductor device of claim 4 , wherein the first dielectric layer comprises silicon oxide.

6 . A semiconductor device, comprising:

a substrate;

a first dielectric layer positioned on the substrate;

a second dielectric layer positioned on the first dielectric layer;

a conductive structure comprising:

a bottom portion positioned along the first dielectric layer and on the substrate; and

a top portion positioned along the second dielectric layer and on the bottom portion; and

an intervening layer positioned between the first dielectric layer and the second dielectric layer, wherein the intervening layer is positioned above the bottom portion of the conductive structure;

wherein the second dielectric layer has etching selectivity to the intervening layer;

wherein the intervening layer comprises silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof.

7 . The semiconductor device of claim 6 , wherein a width of the bottom portion of the conductive structure is less than a width of the top portion thereof.

8 . The semiconductor device of claim 7 , wherein the first dielectric layer and the second dielectric layer comprise a same material.

9 . The semiconductor device of claim 7 , wherein the first dielectric layer and the second dielectric layer comprise different materials.

10 . The semiconductor device of claim 9 , wherein the first dielectric layer comprises silicon oxide.