IP Library › Granted Patent US 12685103
Granted Patent B2
US 12685103 · App. 18/190,175 · Granted Jul 14, 2026

Metal wires with expanded sidewalls

Inventors: Oscar van der Straten (Guilderland Center, NY); Willie Lester Muchrison, Jr. (Troy, NY); Chih-Chao Yang (Glenmont, NY)
Assignee: International Business Machines Corporation
H10W20/033H10W20/057H10W20/076H10W20/425
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Quick Facts
Patent No.
US 12685103
App. No.
18/190,175
Granted
Jul 14, 2026
Kind
B2
Abstract

A semiconductor structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a third region vertically aligned above a second region vertically aligned above a first region, the third region includes three sections: an upper section including a first width; a middle section including an upper horizontal surface including the first width and a lower horizontal surface including a second width; and a lower section including the second width; where the first width is less than the second width; and the second region including a third width at an upper horizontal surface of the second region and a fourth width at a lower horizontal surface of the second region, where the third width is greater than the fourth width.

Claims (37)

1 . A semiconductor structure comprising:

a homogeneous interconnect structure embedded in a dielectric layer, wherein the homogeneous interconnect structure comprises a third region vertically aligned above a second region vertically aligned above a first region;

the third region comprises a first width at a topmost horizontal surface of the third region and a second width at a bottommost horizontal surface of the third region, wherein the first width is less than the second width, wherein at least a portion of the third region comprises a substantially uniform width relative to height;

the second region comprises a third width at an upper horizontal surface of the second region and a fourth width at a lower horizontal surface of the second region, wherein the third width is greater than the fourth width; and

a barrier layer comprising a first material and a second material, wherein only the first material separates the first region and the second region of the homogeneous interconnect structure from the dielectric layer, and wherein only the second material separates the third region of the homogeneous interconnect structure from the dielectric layer.

2 . The semiconductor structure according to claim 1 , further comprising:

a barrier layer separating the homogeneous interconnect structure from the dielectric layer.

3 . The semiconductor structure according to claim 1 , further comprising:

a barrier layer separating the homogeneous interconnect structure from the dielectric layer, wherein the barrier layer comprises a first portion made from a first material and a second portion made from a second material, wherein the first material is different from the second material.

4 . The semiconductor structure according to claim 1 , wherein the dielectric layer comprises at least two different dielectric materials.

5 . The semiconductor structure according to claim 1 , wherein the second width and the third width are substantially similar.

6 . A semiconductor structure comprising:

a homogeneous interconnect structure embedded in a dielectric layer, wherein the homogeneous interconnect structure comprises a third region vertically aligned above a second region vertically aligned above a first region;

the third region comprises three sections: an upper section comprising a first width; a middle section comprising an upper horizontal surface comprising the first width and a lower horizontal surface comprising a second width; and a lower section comprising the second width; wherein the first width is less than the second width; and

the second region comprises a third width at an upper horizontal surface of the second region and a fourth width at a lower horizontal surface of the second region, wherein the third width is greater than the fourth width.

7 . The semiconductor structure according to claim 6 , further comprising:

a barrier layer separating the homogeneous interconnect structure from the dielectric layer.

8 . The semiconductor structure according to claim 6 , further comprising:

a barrier layer separating the homogeneous interconnect structure from the dielectric layer, wherein the barrier layer comprises at least two different materials.

9 . The semiconductor structure according to claim 6 , further comprising:

a barrier layer comprising a first portion and a second portion, wherein the first portion separates both the first region and the second region from the dielectric layer, and wherein the second portion separates the third region from the dielectric layer, wherein the first portion of the barrier layer is made from a different material than the second portion of the barrier layer.

10 . The semiconductor structure according to claim 6 , wherein the dielectric layer comprises at least two different dielectric materials.

11 . The semiconductor structure according to claim 6 , wherein the second width and the third width are substantially similar.

12 . The semiconductor structure according to claim 6 , wherein an average width of the second region and the third region is greater than a width of the first region.

13 . A semiconductor structure comprising:

a set of homogeneous interconnect structures embedded in a dielectric layer with a pitch less than 30 nm, wherein the set of homogeneous interconnect structures each comprise a third region vertically aligned above a second region vertically aligned above a first region;

the third region comprises a first width at an upper horizontal surface of the third region and a second width at a lower horizontal surface of the third region, wherein the first width is less than the second width; and

the second region comprises a third width at an upper horizontal surface of the second region and a fourth width at a lower horizontal surface of the second region, wherein the third width is greater than the fourth width.

14 . The semiconductor structure according to claim 13 , further comprising:

a barrier layer separating the set of homogeneous interconnect structures from the dielectric layer.

15 . The semiconductor structure according to claim 13 , further comprising:

a barrier layer separating the set of homogeneous interconnect structures from the dielectric layer, wherein the barrier layer comprises at least two different materials.

16 . The semiconductor structure according to claim 13 , further comprising:

a barrier layer comprising a first material and a second material, wherein the first material separates both the first region and the second region from the dielectric layer, and wherein the second material separates the third region from the dielectric layer.

17 . The semiconductor structure according to claim 13 , wherein the dielectric layer comprises at least two different dielectric materials.

18 . The semiconductor structure according to claim 13 , wherein the second width and the third width are substantially similar.

19 . The semiconductor structure according to claim 13 , wherein an average width of the first region and the second region is greater than a width of the third region.