Contact for electronic component

1 . A method of manufacturing a contact on a semiconductor region of an electronic component, comprising:

forming a stack of layers that are electrically conductive on lateral walls and at a bottom of an orifice crossing a dielectric region of the electronic component along a longitudinal direction;

wherein the bottom of the orifice is aligned with the semiconductor region;

wherein forming the stack of layers is carried out from a first surface of said dielectric region and comprises:

forming a polysilicon layer and a layer of a first metal in contact with the polysilicon layer, said first metal being selected from the group of transition metals suitable for forming with the polysilicon a metal silicide; and

then performing a thermal anneal to cause the first metal to react with the polysilicon layer to form a layer of metal silicide;

wherein the layer of metal silicide includes at least a portion extending in the longitudinal direction of the orifice; and

wherein the layer of the first metal is formed before the polysilicon layer on lateral walls and at the bottom of the orifice.

2 . The method according to claim 1 , wherein the electronic component comprises a silicide interface layer providing an interface between said semiconductor region and the contact, and wherein the bottom of the orifice emerges onto said silicide interface layer.

3 . The method according to claim 1 , wherein the thermal anneal is carried out at a temperature in a range from 500° C. to 850° C., and for a duration in a range from 30 seconds to 5 minutes.

4 . The method according to claim 1 , wherein forming further comprises forming a diffusion barrier layer before the layer of the first metal and wherein said layer of the first metal is in contact with the diffusion barrier layer.

5 . The method according to claim 4 , wherein forming comprises a step of etching, at least at the bottom of the orifice, a portion of the diffusion barrier layer, the step of etching being before the forming of the layer of the first metal.

6 . The method according to claim 4 , wherein forming further comprises forming a bonding layer on the lateral walls and at the bottom of the orifice before the diffusion barrier layer and in contact with said diffusion barrier layer.

7 . The method according to claim 6 , wherein:

the bonding layer is made of a material selected from the group consisting of:

titanium, cobalt, or nickel; and

the diffusion barrier layer is made of a material selected from the group consisting of: titanium nitride and a tantalum/tantalum nitride bilayer.

8 . The method according to claim 1 , wherein forming further comprises forming a bonding layer on the lateral walls and at the bottom of the orifice before the layer of the first metal and wherein said layer of the first metal is in contact with the bonding layer.

9 . The method according to claim 1 , wherein forming the polysilicon layer comprises filling the orifice.

10 . The method according to claim 1 , further comprising planarizing the layers of the stack in order to make the contact flush with the first surface of the dielectric region, wherein planarizing comprises performing a chemical-mechanical polishing.

11 . The method according to claim 1 , wherein said electronic component comprises a transistor arranged inside and on top of a substrate, the transistor comprising a gate semiconductor region covering a channel region located between a drain semiconductor region and a source semiconductor region, said at least one contact being arranged on one of the drain semiconductor region, the source semiconductor region, and the gate semiconductor region, and wherein a silicide interface layer is interposed between said semiconductor region and the contact.

12 . The method according to claim 1 , wherein:

the first metal is selected from the group consisting of: titanium, cobalt, platinum, nickel, or tungsten; and

the metal silicide is selected from the group consisting of: a titanium silicide, a cobalt silicide, a platinum silicide, a nickel silicide, or a tungsten silicide.

13 . A method of manufacturing a contact on a semiconductor region of an electronic component, comprising:

forming an orifice crossing a dielectric region of the electronic component, said orifice exposing the semiconductor region;

forming a stack of layers that are electrically conductive on lateral walls and at a bottom of the orifice;

wherein forming the stack of layers comprises:

forming a layer of a first metal on the lateral walls and bottom of the orifice;

forming a polysilicon layer on the layer of the first metal;

wherein the first metal is selected from the group consisting of titanium, cobalt, platinum, nickel and tungsten; and

then performing a thermal anneal to cause a reaction between the first metal and the polysilicon layer to form a layer of metal silicide;

wherein the layer of metal silicide includes at least a portion extending in a longitudinal direction of the orifice.

14 . The method according to claim 13 , wherein forming further comprises forming a diffusion barrier layer in said orifice before forming the layer of the first metal.

15 . The method according to claim 14 , further comprising etching a portion of the diffusion barrier layer before forming the layer of the first metal.

16 . The method according to claim 14 , further comprising forming a bonding layer on the lateral walls and bottom of the orifice before forming the diffusion barrier layer.

17 . The method according to claim 16 , further comprising etching a portion of the bonding layer before forming the layer of the first metal.

18 . The method according to claim 13 , wherein forming the polysilicon layer comprises filling the orifice.

19 . The method according to claim 13 , wherein said electronic component comprises a transistor arranged inside and on top of a substrate, the transistor comprising a gate semiconductor region covering a channel region located between a drain semiconductor region and a source semiconductor region, said at least one contact being arranged on one of the drain semiconductor region, the source semiconductor region, and the gate semiconductor region, and wherein a silicide interface layer is interposed between said semiconductor region and the contact.