Method to improve interconnect coefficient of thermal expansion
The present technology includes semiconductor processing methods and devices with improved expansion of the bulk material in substrate features. Methods include cleaning a substrate that is formed from silicon oxide and that defines one or more features and that includes a liner that extends across the silicon oxide and within one or more features and a copper-containing layer deposited on the liner and extending within the one or more features. Methods include depositing a second metal over the substrate, where the second metal has a coefficient of thermal expansion of greater than or about 17. Methods also include diffusing the second metal into the copper containing layer to form a copper alloy.
1 . A semiconductor processing method comprising:
cleaning a substrate, wherein the substrate comprises:
silicon oxide defining one or more features,
a liner extending across the silicon oxide and within the one or more features, and
a copper-containing layer deposited on the liner and extending within the one or more features;
depositing a second metal over the substrate, wherein the second metal has a coefficient of thermal expansion of greater than or about 17;
diffusing the second metal into the copper-containing layer; and
annealing the second metal into the copper-containing layer at a temperature of less than 350° C. to form a copper-alloy.
2 . The method of claim 1 , wherein the copper-containing layer is deposited in one or more features comprising a height to width aspect ratio of greater than or about 6:1.
3 . The method of claim 1 , wherein the substrate further comprises an organic film.
4 . The method of claim 1 , wherein the copper-alloy extrudes greater than or about 1 nm at the annealing temperature of less than 350° C.
5 . The method of claim 1 , further comprising an anneal process at a temperature of less than or about 330° C.
6 . The method of claim 1 , wherein the copper-alloy has a coefficient of thermal expansion that is at least about 20% greater than a coefficient of thermal expansion of copper.
7 . The method of claim 6 , wherein the coefficient of thermal expansion of the copper-alloy is at least about 40% greater than the coefficient of thermal expansion of copper.
8 . The method of claim 1 , wherein the second metal is tin, aluminum, nickel, lead, zinc, or a combination thereof.
9 . The method of claim 1 , further comprising polishing the substrate after forming the copper-alloy.
10 . The method of claim 1 , wherein the cleaning includes a deoxidation treatment.
11 . The method of claim 10 , wherein the cleaning is an in-situ module.
12 . The method of claim 11 , wherein the method includes transferring the substrate under vacuum from the in-situ cleaning module to a deposition chamber configured to deposit the second metal.
13 . The method of claim 12 , wherein the deposition chamber is a chemical vapor deposition chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, a thermally enhanced chemical vapor deposition chamber, a plasma-enhanced chemical vapor deposition chamber, an electroless deposition chamber, or a plasma enhanced atomic layer deposition chamber.
14 . A semiconductor processing method comprising:
etching one or more features having a first side, a second side, a bottom, and a height to width aspect ratio of greater than or about 6:1 in a substrate, wherein the substrate comprises silicon oxide;
forming a liner extending across the silicon oxide and within the one or more features, and depositing a copper-containing layer on the liner and extending within the one or more features;
deoxidizing the copper-containing layer;
depositing a second metal over the copper-containing layer, wherein the second metal has a coefficient of thermal expansion of greater than or about 17; and
annealing the second metal into the copper-containing layer at an annealing temperature of less than 350° C. to form a copper-alloy.
15 . The method of claim 14 , wherein the copper-alloy extrudes greater than or about 1 nm at the annealing temperature of less than 350° C.