Octagonal interconnect wiring for advanced logic
A chip is manufactured using a method for forming a back-end-of-line (BEOL) layer on an IC chip surface comprises providing a first layer on top of a substrate layer of the IC chip, the first layer comprising a bottom portion of a metallic fill region having a first width as seen in a vertical cross-section of the IC chip. The method further provides a second layer on top of the first layer. The second layer comprises a middle portion of the metallic fill region having a second width that is wider than the bottom portion of the metallic fill region. The method provides a third layer on top of the second layer. The third layer comprises a top portion of the metallic fill region having a third width as seen in the vertical cross-section of the IC chip that is narrower than the middle portion of the metallic fill region.
1 . An integrated circuit (IC) chip comprising:
a substrate;
a back-end-of-line (BEOL) layer on top of the substrate, wherein the BEOL comprises an octagonal metal fill region having an octagonal cross-sectional shape that is bounded on its sides by dielectric material; and
a metal liner separating the metal fill region from the dielectric material, wherein the metal liner comprises:
a lower component separating a metal fill region lower portion from the dielectric material;
a middle component separating a metal fill region middle portion from the dielectric material;
an upper component separating a metal fill region upper portion from the dielectric material; and
the lower component, the middle component, and the upper component comprise materials that are different from one another.
2 . The IC chip of claim 1 , wherein the octagonal metal fill region comprises a same material.
3 . The IC chip of claim 1 , wherein the BEOL layer comprises a plurality of octagonal metal fill regions having a pitch dimension below 30 nm.
4 . The IC chip of claim 1 , wherein:
a lower sidewall of the octagonal metal fill region has an angle between 120° and 150° with a horizontal planar layer of the IC chip;
an upper sidewall of the octagonal metal fill region has an angle between 30° and 60° with a horizontal planar layer of the IC chip; and
a middle sidewall of the octagonal metal fill region has an angle of 90° with a horizontal planar layer of the IC chip.
5 . The IC chip of claim 1 , wherein the metal liner comprises at least one material selected from the group consisting of TaN, WN, and MoN.
6 . The IC chip of claim 1 , wherein the metal liner comprises at least two materials selected from the group consisting of TaN, WN, and MoN.
7 . The IC chip of claim 1 , wherein the dielectric material is selected from the group consisting of an organic polymer low-k dielectric and an SiCO-based low-k dielectric.
8 . The IC chip of claim 7 , wherein the organic polymer low-k dielectric is parylene and the SiCO-based low-k dielectric is selected from the group consisting of SiCOH and SiCNOH.
9 . The IC chip of claim 1 , wherein the metal fill region comprises a metal selected from the group consisting of Ru, Pt, W, Co, Mo, Ni, and Rh.
10 . An integrated circuit (IC) chip comprising:
a substrate; and
a back-end-of-line (BEOL) layer on top of the substrate, wherein the BEOL comprises, in vertical cross section, a metal fill region surrounded by a dielectric material and comprising a middle section with a critical dimension that is wider horizontally than an upper section and a lower section of the metal fill region; and
a metal liner separating the metal fill region from the dielectric material, wherein the metal liner comprises:
a lower component separating a metal fill region lower portion from the dielectric material;
a middle component separating a metal fill region middle portion from the dielectric material;
an upper component separating a metal fill region upper portion from the dielectric material; and
the lower component, the middle component, and the upper component comprise materials that are different from one another.
11 . The IC chip of claim 10 , comprising:
a bottom layer, comprising:
the lower section of the metal fill region that is made from a metal selected from the group consisting of: Ru, Pt, W, Co, Mo, Ni, and Rh;
a dielectric material adjacent to two sides of the lower section of the metal fill region comprising an SiCO-based low-k dielectric material; and
a metallic liner portion between the lower section of the metal fill region and the horizontally-adjacent dielectric material, the metallic liner portion comprising WN;
a middle layer, comprising:
the middle section of the metal fill region that is made from a metal selected from the group consisting of: Ru, Pt, W, Co, Mo, Ni, and Rh;
a dielectric material adjacent to two sides of the middle section of the metal fill region comprising parylene; and
a metallic liner portion between the middle section of the metal fill region and the horizontally-adjacent dielectric material, the metallic liner portion comprising TaN; and
an upper layer, comprising:
the upper section of the metal fill region that is made from a metal selected from the group consisting of: Ru, Pt, W, Co, Mo, Ni, and Rh;
a dielectric material adjacent to two sides of the upper section of the metal fill region comprising an SiCO-based low-k dielectric material; and
a metallic liner portion between the upper section of the metal fill region and the horizontally-adjacent dielectric material, the metallic liner portion comprising MoN.