Semiconductor structures including metal wires with edge curvature

1 . A semiconductor structure comprising:

a bottom substrate;

a plurality of metal wires, wherein the plurality of metal wires directly contact the bottom substrate; and

at least one dielectric substrate surrounding the plurality of metal wires, wherein each of the plurality of metal wires includes a tapered upper portion, a tapered lower portion, and a middle portion between the tapered upper portion and the tapered lower portion that is wider than the tapered upper portion and the tapered lower portion, and wherein the at least one dielectric substrate includes

a first dielectric substrate comprising a first material containing a low-k dielectric material with a density gradient adjacent the tapered lower portion of each metal wire,

a second dielectric substrate comprising a second material containing a dielectric material, and

a third dielectric substrate comprising a third material containing a low-k dielectric material with an inverse density gradient adjacent the tapered upper portion of each metal wire,

wherein the second dielectric substrate is located between the first dielectric substrate and the third dielectric substrate.

2 . The semiconductor structure of claim 1 , wherein each of the plurality of metal wires includes a barrier layer, and a metal fill.

3 . The semiconductor structure of claim 2 , wherein the metal fill is a material selected from a group consisting of ruthenium, tungsten, cobalt, iridium and rhodium.

4 . The semiconductor structure of claim 2 , wherein the barrier layer is a material selected from a group consisting of titanium nitride, tantalum nitride and niobium nitride.

5 . The semiconductor structure of claim 1 , wherein the middle portion of each of the plurality of metal wires includes a locally widened critical dimension of the plurality of metal wires.

6 . The semiconductor structure of claim 1 , wherein a pitch between the plurality of metal wires is below 30 nanometers.

7 . The semiconductor structure of claim 1 , wherein the plurality of metal wires each include a plurality of metal fill layers each including portions thereof having a low aspect ratio.

8 . A semiconductor structure comprising:

a bottom substrate;

a plurality of metal wires, wherein the plurality of metal wires directly contact the bottom substrate; and

at least one dielectric substrate surrounding the plurality of metal wires,

wherein each of the plurality of metal wires includes a curved upper portion, a curved lower portion, and a middle portion between the curved upper portion and the curved lower portion that includes a substantially straight sidewall that is wider than the curved upper portion and the curved lower portion, and wherein the at least one dielectric substrate includes

a first dielectric substrate comprising a first material containing a low-k dielectric material with a density gradient adjacent the curved lower portion of each metal wire,

a second dielectric substrate comprising a second material containing a dielectric material, and

a third dielectric substrate comprising a third material containing a low-k dielectric material with an inverse density gradient adjacent the curved upper portion of each metal wire,

wherein the second dielectric substrate is located between the first dielectric substrate and the third dielectric substrate.

9 . The semiconductor structure of claim 8 , wherein each of the plurality of metal wires includes a barrier layer, and a metal fill.

10 . The semiconductor structure of claim 9 , wherein the metal fill is a material selected from a group consisting of ruthenium, tungsten, cobalt, iridium and rhodium.

11 . The semiconductor structure of claim 9 , wherein the barrier layer is a material selected from a group consisting of titanium nitride, tantalum nitride and niobium nitride.

12 . The semiconductor structure of claim 8 , wherein the middle portion of each of the plurality of metal wires includes a locally widened critical dimension of the plurality of metal wires.

13 . The semiconductor structure of claim 8 , wherein a pitch between the plurality of metal wires is below 30 nanometers.

14 . The semiconductor structure of claim 8 , wherein the plurality of metal wires each include a plurality of metal fill layers each including portions thereof having a low aspect ratio.