IP Library Granted Patent US 12,685,112
Granted Patent B2
US 12,685,112 · App. 18/368,355 · Granted Jul 14, 2026

Method of forming copper interconnect structure with manganese barrier layer

Inventors: Daniel C. Edelstein (White Plains, NY); Son V. Nguyen (Schenectady, NY); Takeshi Nogami (Schenectady, NY); Deepika Priyadarshini (Guilderland, NY); Hosadurga Shobha (Niskayuna, NY)
Assignee: Adeia Semiconductor Solutions LLC
H10W20/057H10P14/6314H10P14/6938H10P70/27H10W20/033H10W20/035H10W20/037H10W20/038H10W20/043H10W20/047H10W20/048H10W20/049H10W20/054H10W20/062H10W20/065H10W20/076H10W20/077H10W20/081H10W20/42H10W20/425H10W20/43
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Quick Facts
Patent No.
US 12,685,112
App. No.
18/368,355
Granted
Jul 14, 2026
Kind
B2
Abstract

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Claims (38)

1 . A method comprising:

providing a wafer comprising a dielectric layer, wherein the dielectric layer includes an opening defined therein;

using chemical mechanical polishing to expose a top surface of an interconnect structure comprising copper and manganese in the opening, and a top surface of the dielectric layer outside of the opening;

forming a manganese-free metallic capping layer on the exposed top surface of the interconnect structure; and

annealing the wafer to form a self-aligned barrier layer disposed above the manganese-free metallic capping layer, wherein the self-aligned barrier layer comprises manganese and oxygen.

2 . The method of claim 1 , further comprising: prior to the annealing, oxidizing the manganese-free metallic capping layer.

3 . The method of claim 2 , further comprising: after the annealing, etching the wafer to remove residual material from forming the manganese-free metallic capping layer.

4 . The method of claim 1 , wherein the self-aligned barrier layer further comprises silicon.

5 . The method of claim 1 , wherein the manganese-free metallic capping layer comprises nickel.

6 . The method of claim 1 , wherein the manganese-free metallic capping layer comprises cobalt.

7 . The method of claim 1 , wherein the manganese-free metallic capping layer comprises ruthenium.

8 . The method of claim 1 , wherein the interconnect structure comprises a layer comprising cobalt lining the opening.

9 . The method of claim 1 , wherein the interconnect structure comprises a layer comprising tantalum nitride lining the opening.

10 . The method of claim 1 , wherein:

the opening is defined in the dielectric layer by sidewalls and a bottom surface; and

the interconnect structure comprises:

an underlying barrier layer adjacent to (i) the sidewalls and (ii) the bottom surface;

a copper-manganese layer adjacent to the underlying barrier layer; and

a copper body adjacent to the copper-manganese layer and filling a remaining portion of the opening.

11 . A method comprising:

providing a wafer comprising a dielectric layer, wherein the dielectric layer includes an opening defined therein;

using chemical mechanical polishing to expose a top surface of an interconnect structure comprising copper and manganese in the opening, and a top surface of the dielectric layer outside of the opening;

selectively forming a manganese-free metallic capping layer on copper portions of the exposed top surface of the interconnect structure; and

annealing the wafer to form a self-aligned barrier layer disposed above the manganese-free metallic capping layer, wherein the self-aligned barrier layer comprises manganese and oxygen.

12 . The method of claim 11 , further comprising: prior to the annealing, oxidizing the manganese-free metallic capping layer.

13 . The method of claim 12 , further comprising: after the annealing, etching the wafer to remove residual material from forming the manganese-free metallic capping layer.

14 . The method of claim 11 , wherein the self-aligned barrier layer further comprises silicon.

15 . The method of claim 11 , wherein the manganese-free metallic capping layer comprises nickel.

16 . The method of claim 11 , wherein the manganese-free metallic capping layer comprises cobalt.

17 . The method of claim 11 , wherein the manganese-free metallic capping layer comprises ruthenium.

18 . The method of claim 11 , wherein the interconnect structure comprises a layer comprising cobalt lining the opening.

19 . The method of claim 11 , wherein the interconnect structure comprises a layer comprising tantalum nitride lining the opening.

20 . The method of claim 11 , wherein:

the opening is defined in the dielectric layer by sidewalls and a bottom surface; and

the interconnect structure comprises:

an underlying barrier layer adjacent to (i) the sidewalls and (ii) the bottom surface;

a copper-manganese layer adjacent to the underlying barrier layer; and

a copper body adjacent to the copper-manganese layer and filling a remaining portion of the opening.