Local interconnect

1 . A semiconductor structure, comprising:

a first source/drain contact and a second source/drain contact extending lengthwise along a first direction;

a gate structure disposed between the first source/drain contact and the second source/drain contact along a second direction perpendicular to the first direction and extending lengthwise along the first direction; and

a first metal layer disposed over the first source/drain contact, the second source/drain contact, and the gate structure, the first metal layer comprising:

a first metal line disposed over the first source/drain contact and extending along the first direction,

a first gate signal line and a second gate signal line disposed over the gate structure and spaced apart from one another by a gap along the first direction, and

a second metal line disposed over the second source/drain contact and extending along the first direction, wherein the second metal line comprises a branch that partially extends into the gap.

2 . The semiconductor structure of claim 1 , wherein each of the first metal line, the second metal line, the first gate signal line, and the second gate signal line comprises a barrier layer and a metal fill layer over the barrier layer.

3 . The semiconductor structure of claim 2 ,

wherein the barrier layer comprises titanium nitride or tantalum nitride,

wherein the metal fill layer comprises cobalt (Co), ruthenium (Ru), tungsten (W), copper (Cu), nickel (Ni), or a combination thereof.

4 . The semiconductor structure of claim 1 , further comprising:

a first source/drain contact via extending vertically between the first source/drain contact and the first metal line;

a second source/drain contact via extending vertically between the second source/drain contact and the second metal line; and

a gate contact via extending vertically between the gate structure and the branch of the second metal line.

5 . The semiconductor structure of claim 1 , wherein the first metal line, the second metal line, the first gate signal line, and the second gate signal line are disposed in an etch stop layer (ESL) and a dielectric layer disposed over the ESL.

6 . The semiconductor structure of claim 1 ,

wherein the gap comprises a width along the first direction,

wherein the width is between about 25 nm and about 50 nm.

7 . The semiconductor structure of claim 1 , wherein the first gate signal line and the second gate signal line are aligned along the first direction.

8 . The semiconductor structure of claim 1 ,

wherein the first gate signal line and the second gate signal line comprise a width along the second direction,

Wherein the width is between about 8 nm and about 35 nm.

9 . A semiconductor structure, comprising:

a source/drain contact extending lengthwise along a first direction;

a gate structure adjacent the source/drain contact along a second direction perpendicular to the first direction and extending lengthwise along the first direction;

an etch stop layer (ESL) over the source/drain contact and the gate structure;

a dielectric layer over the ESL;

a first gate signal line and a second gate signal line disposed over the gate structure and spaced apart from one another by a gap along the first direction; and

a metal line disposed over the source/drain contact and extending along the first direction,

wherein the metal line comprises a branch that partially extends into the gap.

10 . The semiconductor structure of claim 9 , wherein the metal line is electrically coupled to the source/drain contact by way of a source/drain contact via that extends vertically between the source/drain contact and the metal line.

11 . The semiconductor structure of claim 10 , wherein the branch of the metal line is electrically coupled to the gate structure by way of a gate contact via that extends vertically between the gate structure and the branch.

12 . The semiconductor structure of claim 11 , wherein the source/drain contact via and the gate contact via are not aligned along the second direction.

13 . The semiconductor structure of claim 10 ,

wherein the first gate signal line and the second gate signal line comprise a width along the second direction,

wherein the branch extends along the second direction across more than one half (½) of the width.

14 . A semiconductor structure, comprising:

a first gate signal line extending along a first direction;

a second gate signal line lengthwise aligned with and spaced apart from the first gate signal line; and

a first metal line extending along the first direction,

wherein the first metal line comprises a branch extending from the first metal line along a second direction perpendicular to the first direction,

wherein the branch partially extends between the first gate signal line and the second gate signal line along the first direction.

15 . The semiconductor structure of claim 14 ,

wherein the first gate signal line and the second gate signal line comprise a width along the second direction,

wherein the branch extends along the second direction across more than one half (½) of the width.

16 . The semiconductor structure of claim 14 , further comprising:

a second metal line extending along the first direction,

wherein the first gate signal line is disposed between the first metal line and the second metal line,

wherein the branch is spaced apart from the second metal line.

17 . The semiconductor structure of claim 16 , wherein the first gate signal line, the second gate signal line, the first metal line, and the second metal line are embedded in an etch stop layer (ESL) and a dielectric layer over the ESL.

18 . The semiconductor structure of claim 16 ,

wherein the first metal line is directly coupled to a drain contact via underlying the first metal line,

wherein the branch is directly coupled to a gate contact via underlying the branch,

wherein the second metal line is directly coupled to a source contact via underlying the second metal line.

19 . The semiconductor structure of claim 18 , wherein the branch is spaced apart from the first gate signal line and the second gate signal line.

20 . The semiconductor structure of claim 18 , wherein the drain contact via, the gate contact via, and the source contact via are not aligned along the second direction.