Semiconductor circuit pattern and manufacturing method thereof
The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer, and a metal layer is filled in the compensation groove.
1 . A semiconductor circuit pattern comprising:
a dielectric layer;
at least one first circuit pattern located in the dielectric layer, wherein from a top view, the first circuit pattern comprises a line part and a compensation part, wherein the line part comprises two straight boundaries and the compensation part comprises two arc boundaries, and the line part is connected with the compensation part, wherein the two arc boundaries of the compensation part are aligned with each other in a horizontal direction; and
a via contact located beside the first circuit pattern, wherein the compensation part of the first circuit pattern does not contact the via contact.
2 . The semiconductor circuit pattern according to claim 1 , wherein a width of the compensation part is greater than a width of the line part.
3 . The semiconductor circuit pattern according to claim 1 , wherein the compensation part has an arc-shaped profile when viewed from a cross section.
4 . The semiconductor circuit pattern according to claim 1 , further comprising a second circuit structure which does not include the compensation part.
5 . The semiconductor circuit pattern according to claim 4 , wherein a bottom surface of the compensation part is lower than a bottom surface of the second circuit structure when viewed from a sectional view.
6 . The semiconductor circuit pattern according to claim 1 , further comprising a metal circuit layer under the dielectric layer, and the first circuit pattern does not directly contact the metal circuit layer.