Reversed high aspect ratio contact (HARC) structure and process

1 . A semiconductor chip architecture comprising:

a first interlayer dielectric (ILD) structure;

a front-end-of-line (FEOL) layer on a first side of the first ILD structure, the FEOL layer comprising a semiconductor device on the first side of the first ILD structure, a shallow trench isolation (STI) structure in the first ILD structure, and a second ILD structure on the semiconductor device and the first ILD structure;

a middle-of-line (MOL) layer provided on the FEOL layer, the MOL layer comprising a contact and a via connected to the contact;

an insulating layer on the first side of the first ILD structure and adjacent to the via in a horizontal direction, a first surface of the insulating layer being coplanar to a first surface of the via; and

a power rail penetrating the first ILD structure from a second side of the first ILD structure opposite to the first side,

wherein the via extends through the second ILD structure, the STI structure, and the first ILD structure in a vertical direction to contact the power rail, a second surface of the via protruding from a second surface of the STI structure,

wherein the semiconductor device comprises gate structures and first spacer layers on side surfaces of the gate structures,

wherein the contact is between adjacent first spacer layers among the first spacer layers and the contact is between side surfaces of adjacent gate structures among the gate structures facing each other in the horizontal direction, and

wherein the gate structure is in direct contact with a second spacer layer that extends in the horizontal direction in a direction perpendicular to the direction in which the first spacer layers extend.

2 . The semiconductor chip architecture of claim 1 , wherein the via is a high aspect ratio contact (HARC) via that penetrates through the second ILD structure and the first ILD structure in the vertical direction to contact the power rail.

3 . The semiconductor chip architecture of claim 1 , wherein the insulating layer extends from a level of a first surface of the contact to a first surface of the STI structure in the vertical direction, and directly contacts a side surface of the via in the horizontal direction.

4 . The semiconductor chip architecture of claim 1 ,

wherein the via is directly adjacent to the second spacer layer in the horizontal direction.

5 . The semiconductor chip architecture of claim 3 , wherein the insulating layer comprises one of silicon nitride (SiN), silicon carbon-nitride (SiCN), and ion doped carbon (C).

6 . A method of manufacturing a semiconductor chip architecture, the method comprising:

forming a substrate including an oxide layer;

forming a semiconductor device and a shallow trench isolation (STI) structure on a first side of the substrate;

forming a second interlayer dielectric (ILD) structure on the semiconductor device and the substrate;

patterning the second ILD structure based on a self-align contact (SAC) pattern comprising a first pattern and a second pattern;

etching the second ILD structure and the substrate based on the first pattern to a level of the oxide layer to form a first trench and the ILD structure based on the second pattern to a level of the semiconductor device to form second trenches based on the SAC pattern;

filling the first trench and the second trenches with at least one metal material to form a via and contacts, respectively; and

flipping the substrate wherein a second side of the substrate that is opposite the first side of the substrate is exposed;

etching the substrate to expose the via and the semiconductor device;

forming a first ILD structure on the semiconductor device and on a side surface of the via,

forming a power rail penetrating the first ILD structure from a top side of the first ILD structure such that the power rail contacts the via;

prior to etching the first trench, etching the second ILD structure to a level of the first side of the STI structure to form a third trench; and

filling the third trench with an insulating material to form an insulating layer;

wherein the semiconductor device comprises gate structures and first spacer layers on side surfaces of the gate structures,

wherein the contact is between adjacent first spacer layers among the first spacer layers and the contact is between side surfaces of adjacent gate structures among the gate structures facing each other in a horizontal direction, and

wherein the gate structures are in direct contact with a second spacer layer that extends in the horizontal direction in a direction perpendicular to the direction in which the first spacer layers extend.

7 . The method of claim 6 , wherein the via is formed adjacent to the insulating layer.

8 . The method of claim 7 , wherein the second trenches are etched based on the second pattern formed based on the first spacer layers and the first trench.

9 . The method of claim 6 , wherein the first trench is further etched such that the second spacer layer horizontally extends in a direction perpendicular to a direction in which the first spacer layers extend.

10 . The method of claim 6 , further comprising:

forming a gate poly cut pattern extending in a direction perpendicular to a direction in which gate structures extend and between gate structures.

11 . The method of claim 10 , wherein the first trench is etched based on the first pattern formed based on the gate poly cut pattern and first spacer layers directly provided on side surfaces of the gate structures.

12 . The method of claim 11 , wherein the second trenches are etched based on the second pattern formed based on the first spacer layers and the first trench.

13 . The method of claim 11 , wherein the via is formed directly adjacent to the gate poly cut pattern.

14 . The semiconductor chip architecture of claim 1 , wherein the first spacer layers are in contact with the second spacer layer.

15 . The method of claim 6 , wherein the first spacer layers are in contact with the second spacer layer.