Gallium nitride (GaN) devices with through-silicon vias
Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.
1 . An integrated circuit structure, comprising:
a layer comprising gallium and nitrogen, the layer comprising gallium and nitrogen above a silicon substrate;
a backside structure below the silicon substrate and opposite the layer comprising gallium and nitrogen, the backside structure including conductive features and dielectric structures; and
a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer comprising gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.
2 . The integrated circuit structure of claim 1 , wherein the essentially vertical portion is in the layer comprising gallium and nitrogen, and the tapered portion is in the silicon substrate.
3 . The integrated circuit structure of claim 1 , wherein the tapered portion is defined by Si(111) crystal planes.
4 . The integrated circuit structure of claim 1 , wherein individual ones of the through-silicon via power bars comprise a dielectric liner and a copper fill.
5 . The integrated circuit structure of claim 1 , further comprising a layer comprising conductive features above the layer comprising gallium and nitrogen, wherein individual ones of the through-silicon via power bars extend to a corresponding one of the conductive features of the layer.
6 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a layer comprising gallium and nitrogen, the layer comprising gallium and nitrogen above a silicon substrate;
a backside structure below the silicon substrate and opposite the layer comprising gallium and nitrogen, the backside structure including conductive features and dielectric structures; and
a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer comprising gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.
7 . The computing device of claim 6 , further comprising:
a memory coupled to the board.
8 . The computing device of claim 6 , further comprising:
a power delivery chip coupled to the board.
9 . The computing device of claim 6 , further comprising:
a camera coupled to the board.
10 . The computing device of claim 6 , wherein the component is a packaged integrated circuit die.
11 . An integrated circuit structure, comprising:
a layer comprising gallium and nitrogen, the layer comprising gallium and nitrogen above a silicon substrate;
a backside structure below the silicon substrate and opposite the layer comprising gallium and nitrogen, the backside structure including conductive features and dielectric structures; and
a waveguide structure including a plurality of through-silicon vias having a co-planar arrangement, individual ones of the through-silicon vias extending through the layer comprising gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon vias having a tapered portion coupled to an essentially vertical portion.
12 . The integrated circuit structure of claim 11 , wherein the essentially vertical portion is in the layer comprising gallium and nitrogen, and the tapered portion is in the silicon substrate.
13 . The integrated circuit structure of claim 11 , wherein the tapered portion is defined by Si(111) crystal planes.
14 . The integrated circuit structure of claim 11 , wherein individual ones of the through-silicon vias comprise a dielectric liner and a copper fill.
15 . The integrated circuit structure of claim 11 , further comprising a layer comprising conductive features above the layer comprising gallium and nitrogen, wherein individual ones of the through-silicon vias extend to a corresponding one of the conductive features of the layer.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a layer comprising gallium and nitrogen, the layer comprising gallium and nitrogen above a silicon substrate;
a backside structure below the silicon substrate and opposite the layer comprising gallium and nitrogen, the backside structure including conductive features and dielectric structures; and
a waveguide structure including a plurality of through-silicon vias having a co-planar arrangement, individual ones of the through-silicon vias extending through the layer comprising gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon vias having a tapered portion coupled to an essentially vertical portion.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a power delivery chip coupled to the board.
19 . The computing device of claim 16 , further comprising:
a camera coupled to the board.
20 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.