Via structure and method for forming the same
A via structure, a semiconductor structure, and methods for forming the via structure and the semiconductor structure are presented. A via structure includes a first conductive portion through an interconnect structure, a second conductive portion through a substrate and in contact with the first conductive portion, and a liner layer. The liner layer is between the first conductive portion and the interconnect structure, and between the second conductive portion and the substrate. The liner layer includes a portion extending parallel to a surface of the substrate.
1 . A via structure, comprising:
a first conductive portion through an interconnect structure;
a second conductive portion through a substrate and in contact with the first conductive portion;
a third conductive portion through the interconnect structure and in contact with the second conductive portion; and
a liner layer between the first conductive portion and the interconnect structure, and between the second conductive portion and the substrate,
wherein the liner layer comprises a portion extending parallel to a surface of the substrate.
2 . The via structure of claim 1 ,
wherein the first conductive portion further extends through a semiconductor layer between the interconnect structure and the substrate, and
wherein the portion of the liner layer extends between the second conductive portion and the semiconductor layer.
3 . The via structure of claim 2 , wherein an interface between the first conductive portion and the second conductive portion levels with an interface between the substrate and the semiconductor layer.
4 . The via structure of claim 1 , wherein a diameter of the first conductive portion is smaller than a diameter of the second conductive portion.
5 . The via structure of claim 4 ,
wherein, along a direction parallel to the surface of the substrate, the diameter of the first conductive portion is in a range of about 50 nm to about 5 μm, and
wherein, along the direction parallel to the surface of the substrate, the diameter of the second conductive portion is in a range of about 1 μm to about 100 μm.
6 . The via structure of claim 1 ,
wherein the first conductive portion and the second conductive portion each extends in a direction perpendicular to the surface of the substrate, and
wherein, on a plane parallel to the surface of the substrate, a projection of the first conductive portion is within a projection of the second conductive portion.
7 . The via structure of claim 1 ,
wherein the portion is a first portion,
wherein the liner layer further comprises a second portion extending perpendicular to the surface of the substrate, and
wherein a thickness of the second portion of the liner layer is in a range of about 0.1 μm to about 5 μm.
8 . The via structure of claim 1 , wherein the liner layer comprises silicon oxide.
9 . The via structure of claim 1 , wherein the portion of the liner layer extends laterally between a sidewall of the first conductive portion and a sidewall of the third conductive portion.
10 . A semiconductor structure, comprising:
a substrate;
a semiconductor layer over the substrate;
an interconnect structure over the semiconductor layer;
a via structure through the substrate, semiconductor layer, and the interconnect structure; and
a transistor in the semiconductor layer,
wherein the via structure comprises:
a first conductive portion through the interconnect structure and the semiconductor layer,
a second conductive portion in contact with the first conductive portion and through the substrate, and
a third conductive portion in contact with the second conductive portion,
wherein the transistor is disposed directly over the second conductive portion, and
wherein the third conductive portion extends alongside the first conductive portion through the interconnect structure.
11 . The semiconductor structure of claim 10 ,
wherein the first conductive portion and the second conductive portion are cylindrical in shape, and
wherein a diameter of the first conductive portion is smaller than a diameter of the second conductive portion.
12 . The semiconductor structure of claim 10 ,
wherein the first conductive portion and the second conductive portion each extend in a direction perpendicular to a surface of the substrate, and
wherein, on a plane parallel to the surface of the substrate, a projection of the first conductive portion is within the projection of the second conductive portion.
13 . The semiconductor structure of claim 10 , further comprising:
a first liner layer between the second conductive portion and the substrate,
wherein the first liner layer comprises a portion disposed between the top surface of the second conductive portion and the semiconductor layer.
14 . The semiconductor structure of claim 13 , further comprising:
a second liner layer extending from between the first conductive portion and the interconnect structure to between the first conductive portion and the semiconductor layer,
wherein the second liner layer is in contact with the first liner layer.
15 . The semiconductor structure of claim 14 ,
wherein the first liner layer comprises a sidewall portion disposed between a sidewall of the second conductive portion and the substrate, and
wherein a thickness of the sidewall portion is greater than a thickness of the second liner layer.
16 . The semiconductor structure of claim 10 , further comprising
a die structure is disposed between the second conductive portion and the third conductive portion.
17 . The semiconductor structure of claim 10 ,
wherein, on a plane parallel to a surface of the substrate, a projection of the first conductive portion and a projection of the third conductive portion are symmetric about a geographic center of the second conductive portion.
18 . A semiconductor structure, comprising:
a substrate;
a semiconductor layer overlaying the substrate;
an interconnect structure overlaying the semiconductor layer; and
a via structure, comprising:
a first upper portion and a second upper portion extending through the semiconductor layer and the interconnect structure, wherein the first upper portion and the second upper portion are separated along a lateral direction,
a lower portion extending through the substrate and coupled to the first upper portion and the second upper portion, and
a liner extending along a sidewall of the lower portion and a sidewall of one of the first upper portion and the second upper portion.
19 . The semiconductor structure of claim 18 , wherein the liner extends along portions of a top surface of the lower portion.
20 . The semiconductor structure of claim 18 ,
wherein the semiconductor structure further comprises a transistor disposed over the semiconductor layer, and
wherein the transistor is interposed between the first upper portion and the second upper portion along the lateral direction.