Method and structure of forming barrier-less skip via with subtractive metal patterning
A microelectronic structure including a first metal line, a second metal line, and a third metal line. A skip-via connecting the first metal line to the third metal line, where the skip-via includes a bottom section and a top section. A bottom sidewall of the bottom section is at a first angle and a top sidewall of the top section are at a second angle, where the first angle and the second angle are opposite from each other.
1 . A microelectronic structure comprising:
a first metal line, a second metal line, and a third metal line;
a skip-via connecting the first metal line to the third metal line, wherein the skip-via includes a bottom section and a top section, wherein a bottom sidewall of the bottom section is at a first angle and a top sidewall of the top section are at a second angle, wherein the first angle and the second angle are opposite from each other; and
an interlayer dielectric layer located around the first metal line and the bottom section of the skip via, wherein a bottom surface of the top section of the skip via is in contact with a top surface of the interlayer dielectric layer.
2 . The microelectronic structure of claim 1 , wherein a cross-section of the skip via has a diamond shape profile.
3 . The microelectronic structure of the claim 1 , wherein the bottom section of the skip-via has a bottom surface in contact with the first metal line, wherein the bottom surface has a first width.
4 . The microelectronic structure of claim 3 , wherein the bottom section of the skip-via has a top surface in contact with a bottom surface of the top section of the skip-via, wherein the top surface of the bottom section has a second width.
5 . The microelectronic structure of claim 4 , wherein the second width is larger than the first width.
6 . The microelectronic structure of the claim 5 , wherein the top section of the skip-via has a bottom surface in contact with top surface of the bottom section of the skip via, wherein the bottom surface of the top section has a third width.
7 . The microelectronic structure of claim 6 , wherein the top section of the skip-via has a top surface connected with a bottom surface of the third metal line, wherein the top surface of the top section has a fourth width.
8 . The microelectronic structure of claim 7 , wherein the third width is larger than the fourth width.
9 . The microelectronic structure of claim 7 , wherein the third width is larger than the second width.
10 . The microelectronic structure of claim 7 , wherein the third width is substantially equal to the second width.
11 . The microelectronic structure of claim 1 , wherein the first angle of bottom sidewalls of the bottom section of skip-via are angled away from a center line of the skip-via as the bottom sidewalls extend vertically up the bottom section of the skip-via.
12 . The microelectronic structure of claim 2 , wherein the second angle of top sidewalls of the top section of skip-via are angled towards the center line of the skip-via as the top sidewalls extend vertically up the top section of the skip-via.
13 . A microelectronic device comprising:
a first metal line, a second metal line, and a third metal line;
a skip-via connecting the first metal line to the third metal line, wherein the skip-via includes a bottom section and a top section, wherein a bottom sidewall of the bottom section is at a first angle and a top sidewall of the top section are at a second angle, wherein the first angle and the second angle are opposite from each other;
an interlayer dielectric layer located around the first metal line and the bottom section of the skip via, wherein a bottom surface of the top section of the skip via is in contact with a top surface of the interlayer dielectric layer; and
a liner located between the third metal line and the top section of the skip via.
14 . The microelectronic device of the claim 13 , wherein the bottom section of the skip-via has a bottom surface in contact with the first metal line, wherein the bottom surface has a first width, wherein the bottom section of the skip-via has a top surface in contact with a bottom surface of the top section of the skip-via, and wherein the top surface of the bottom section has a second width.
15 . The microelectronic device of the claim 14 , wherein the top section of the skip-via has a bottom surface in contact with top surface of the bottom section of the skip via, wherein the bottom surface of the top section has a third width, wherein the top section of the skip-via has a top surface connected with a bottom surface of the liner, and wherein the top surface of the top section has a fourth width.
16 . The microelectronic device of claim 15 , wherein the second width is larger than the first width, and wherein the third width is larger than the fourth width.
17 . The microelectronic device of claim 16 , wherein the third width is larger than the second width.
18 . The microelectronic device of claim 17 , wherein the third width is substantially equal to the second width.
19 . A method comprising:
forming a first metal line;
forming an interlayer dielectric layer located around the first metal line;
forming a second metal layer and patterning the second metal layer to form a second metal line and a skip-via; and
forming a third metal line; and
wherein the skip-via connects the first metal line to the third metal line, wherein the skip-via includes a bottom section and a top section, wherein a bottom sidewall of the bottom section is at a first angle and a top sidewall of the top section are at a second angle, wherein the first angle and the second angle are opposite from each other, wherein the interlayer dielectric layer is located around the bottom section of the skip via, wherein a bottom surface of the top section of the skip via is in contact with a top surface of the interlayer dielectric layer.
20 . The method of claim 19 , wherein a cross-section of the skip via has a diamond shape profile.