Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability
Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.
1 . An integrated chip comprising:
a plurality of conductive structures over a substrate;
a first dielectric layer disposed laterally between the conductive structures; and
a spacer structure disposed between the first dielectric layer and the plurality of conductive structures, wherein the spacer structure comprises a lateral segment underlying and contacting a bottom surface of the first dielectric layer;
an etch stop layer over the plurality of conductive structures, wherein the etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer; and
a second dielectric layer over the etch stop layer, wherein the second dielectric layer comprises a vertical segment laterally spaced from the spacer structure by the etch stop layer and having a bottom surface below a top surface of the etch stop layer.
2 . The integrated chip of claim 1 , wherein a thickness of the spacer structure is greater than a thickness of the etch stop layer.
3 . The integrated chip of claim 1 , wherein a sidewall of the etch stop layer contacts a sidewall of the spacer structure at a point below the upper surface of the spacer structure and above the plurality of conductive structures, wherein the sidewall of the etch stop layer is aligned with a sidewall of an individual conductive structure in the plurality of conductive structures.
4 . The integrated chip of claim 1 , wherein the spacer structure comprises a first dielectric material and the etch stop layer comprises a second dielectric material different from the first dielectric material.
5 . The integrated chip of claim 1 , wherein the upper surface of the spacer structure is vertically offset from an upper surface of the plurality of conductive structures by a vertical distance that is greater than a thickness of the etch stop layer.
6 . The integrated chip of claim 1 , further comprising:
a conductive via over an individual conductive structure in the plurality of conductive structures, wherein a lower surface of the conductive via contacts a lateral surface of the spacer structure at a location below the upper surface of the spacer structure and above an upper surface of the individual conductive structure, wherein a bottom surface of the conductive via contacts the upper surface of the individual conductive structure, wherein the conductive via comprises a sidewall vertically extending from the lower surface of the conductive via to the bottom surface of the conductive via, wherein the sidewall of the conductive via contacts a sidewall of the spacer structure.
7 . The integrated chip of claim 1 , wherein the first dielectric layer comprises a plurality of air-gaps spaced between opposing sidewalls of the spacer structure.
8 . An integrated chip comprising:
a plurality of conductive structures over a substrate;
a first dielectric layer disposed laterally between the conductive structures;
a spacer structure disposed between the first dielectric layer and the plurality of conductive structures, wherein a lower surface of the spacer structure is aligned with a lower surface of the plurality of conductive structures, wherein the spacer structure comprises a lateral segment underlying and contacting a bottom surface of the first dielectric layer;
an etch stop layer over the plurality of conductive structures, wherein the etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer; and
a second dielectric layer over the etch stop layer, wherein the second dielectric layer comprises a vertical segment laterally spaced from the spacer structure by the etch stop layer and having a bottom surface below a top surface of the etch stop layer.
9 . The integrated chip of claim 8 , wherein the etch stop layer continuously extends from the upper surface of the spacer structure to a sidewall of the spacer structure.
10 . The integrated chip of claim 8 , wherein the plurality of conductive structures comprises a first conductive structure and a second conductive structure laterally offset from the first conductive structure, wherein the spacer structure comprises a U-shaped segment between the first conductive structure and the second conductive structure.
11 . The integrated chip of claim 10 , wherein the etch stop layer extends along outer opposing sidewalls of the U-shaped segment of the spacer structure.
12 . The integrated chip of claim 8 , wherein the etch stop layer comprises a U-shaped segment above an individual conductive structure in the plurality of conductive structures.
13 . The integrated chip of claim 8 , wherein the upper surfaces of the spacer structure and the first dielectric layer are vertically above upper surfaces of the conductive structures.
14 . The integrated chip of claim 8 , wherein the spacer structure comprises a pair of opposing sidewalls spaced between a pair of adjacent conductive structures in the plurality of conductive structures, wherein a distance between the pair of opposing sidewalls continuously decreases from the upper surface of the spacer structure in a direction towards the substrate.
15 . The integrated chip of claim 8 , further comprising:
a conductive via over an individual conductive structure in the plurality of conductive structures, wherein the conductive via contacts a lateral surface and a sidewall of the spacer structure, wherein the lateral surface of the spacer structure is below the upper surface of the spacer structure.
16 . An integrated chip comprising:
a plurality of conductive structures over a substrate;
a first dielectric layer disposed laterally between the conductive structures;
a spacer structure disposed between the first dielectric layer and the plurality of conductive structures, wherein a height of the spacer structure is greater than a height of the plurality of conductive structures, wherein the spacer structure comprises a lateral segment underlying and contacting a bottom surface of the first dielectric layer;
an etch stop layer over the plurality of conductive structures, wherein the etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer; and
a second dielectric layer over the etch stop layer, wherein the second dielectric layer comprises a vertical segment laterally spaced from the spacer structure by the etch stop layer and having a bottom surface below a top surface of the etch stop layer.
17 . The integrated chip of claim 16 , wherein a sidewall of the etch stop layer is aligned with an outer sidewall of an individual conductive structure in the plurality of conductive structures.
18 . The integrated chip of claim 16 , wherein a height of the first dielectric layer is less than the height of the spacer structure and is greater than the height of the plurality of conductive structures.
19 . The integrated chip of claim 1 , wherein a lower surface of the spacer structure is aligned with a lower surface of the plurality of conductive structures, and wherein a height of the spacer structure is greater than a height of the plurality of conductive structures.
20 . The integrated chip of claim 1 , wherein the vertical segment overlies an individual conductive structure in the plurality of conductive structures, wherein a width of the vertical segment is less than a width of the individual conductive structure.