IP Library Granted Patent US 12685146
Granted Patent B2
US 12685146 · App. 18/333,584 · Granted Jul 14, 2026

Semiconductor device, amplifying device, and method of manufacturing semiconductor device

Inventors: Tsuyoshi Takahashi (Ebina, JP); Kenichi Kawaguchi (Ebina, JP)
Assignee: Fujitsu Limited
H10W20/484H03F1/56H03F3/04H10D30/015H10D30/475H10W20/40H10W44/20H03F2200/222H03F2200/387H10W44/234
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Quick Facts
Patent No.
US 12685146
App. No.
18/333,584
Granted
Jul 14, 2026
Kind
B2
Abstract

A semiconductor device includes a substrate; a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode and the drain electrode being formed on the substrate; a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate; an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires; and an extraction electrode connecting the electrode pad and the gate electrode.

Claims (27)

1 . A semiconductor device, comprising:

a substrate;

a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode and the drain electrode being formed on the substrate;

a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate;

an electrode pad formed at upper ends of the plurality of nonconductive nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nonconductive nanowires; and

an extraction electrode connecting the electrode pad and the gate electrode.

2 . The semiconductor device as claimed in claim 1 , further comprising:

an active region formed on the upper surface of the substrate, wherein the gate electrode, the source electrode, and the drain electrode are formed on an upper surface of the active region, and the active region includes a channel layer and an electron supply layer.

3 . The semiconductor device as claimed in claim 1 , wherein the plurality of nonconductive nanowires are made of non-doped GaAs.

4 . The semiconductor device as claimed in claim 1 , wherein the substrate includes a first layer made of a same material as a material used for the plurality of nonconductive nanowires, and lower ends of the plurality of nonconductive nanowires are in contact with the first layer.

5 . The semiconductor device as claimed in claim 1 , wherein the plurality of nonconductive nanowires are made of semiconductors deactivated by introducing defects.

6 . The semiconductor device as claimed in claim 1 , further comprising:

an insulating film disposed over the substrate, wherein the insulating film includes a gap at positions of the plurality of nanowires such that at least some of the plurality of nonconductive nanowires are not in contact with the insulating film.

7 . The semiconductor device as claimed in claim 1 , wherein the plurality of nonconductive nanowires are made of insulators.

8 . An amplifier circuit comprising:

a substrate;

a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode, and the drain electrode being formed on the substrate;

a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate;

an electrode pad formed at upper ends of the plurality of nonconductive nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nonconductive nanowires;

an extraction electrode connecting the electrode pad and the gate electrode;

a first matching circuit configured to apply an external input signal to the electrode pad; and

a second matching circuit configured to output a signal from the source electrode or the drain electrode to an outside.

9 . A method of manufacturing a semiconductor device, the method comprising:

forming a substrate including a first layer, the first layer being made of a first material;

forming a transistor on the substrate;

forming a plurality of nonconductive nanowires by crystal growth on an upper surface of the first layer, the plurality of nonconductive nanowires being made of the first material; and

forming an electrode pad at upper ends of the plurality of nonconductive nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nonconductive nanowires.