Extended via connect for pixel array
Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.
1 . A method of forming an integrated chip, comprising:
forming a first dielectric layer, a second dielectric layer, and a first etch stop layer separating the first dielectric layer and the second dielectric layer over a substrate, wherein the second dielectric layer is over the first dielectric layer, and wherein the first dielectric layer overlies a first wire and a second wire;
performing a first etch into the first dielectric layer and the second dielectric layer to form a first via opening and a second via opening extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer and respectively exposing the first and second wires;
filling the first and second via openings respectively with a first dielectric plug and a second dielectric plug;
performing a second etch into the second dielectric layer, removing portions of the second dielectric layer surrounding the first via opening to form a wire opening in the second dielectric layer overlapping with the first via opening while the second via opening is masked, wherein the wire opening has a greater width than the first via opening;
removing the first and second dielectric plugs;
filling the first and second via openings and the wire opening by depositing a conductive material in the first via opening, the first wire opening, and the second via opening; and
removing portions of the conductive material above the second dielectric layer, exposing the second dielectric layer, and resulting in a via remaining in the first dielectric layer, a third wire remaining in the second dielectric layer, and an extended via extending from the top surface of the second dielectric layer to the bottom surface of the first dielectric layer,
wherein the extended via has a height greater than or equal to a combined height of the via and the third wire.
2 . The method according to claim 1 , further comprising:
depositing a third dielectric layer covering the third wire and the extended via; and
forming a trench capacitor overlying the third dielectric layer and having a bottom protrusion protruding downward to a fourth wire level with the first and second wires.
3 . The method according to claim 2 , further comprising:
depositing a fourth dielectric layer over the third dielectric layer and the trench capacitor;
performing a third etch through the fourth dielectric layer to form a third via opening exposing the extended via; and
filling the third via opening with conductive material to form a second extended via overlying the extended via and sharing a common height with the extended via.
4 . The method of claim 2 , further comprising forming a second trench capacitor on an opposite side of the extended via as the trench capacitor, wherein the trench capacitor and the second trench capacitor are separated by a distance of less than 0.8 micrometers.
5 . The method according to claim 1 , where during the removal of the first dielectric plug, a portion of the first dielectric layer is removed beneath the wire opening, extending the wire opening into the first dielectric layer.
6 . The method of claim 1 , wherein the first wire and the second wire are spaced in a lateral direction by a fourth wire.
7 . A method of forming an integrated device, the method comprising:
forming a first dielectric layer, a second dielectric layer, and a first etch stop layer separating the first dielectric layer and the second dielectric layer over a substrate, wherein the second dielectric layer is over the first dielectric layer;
forming a first via opening and a second via opening extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer;
removing portions of the second dielectric layer surrounding the first via opening to form a first wire opening in the second dielectric layer;
depositing a conductive material in the first via opening, the first wire opening, and the second via opening; and
removing portions of the conductive material above the second dielectric layer, exposing the second dielectric layer, and resulting in a first via remaining in the first dielectric layer, a first wire remaining in the second dielectric layer, and a first extended via extending from the top surface of the second dielectric layer to the bottom surface of the first dielectric layer.
8 . The method of claim 7 , wherein after depositing the conductive material, the conductive material extends from below the bottom surface of the first dielectric layer to over the top surface of the second dielectric layer by extending through the second via opening.
9 . The method of claim 7 , further comprising:
forming a first capacitor over the substrate, the first capacitor having a protrusion that extends through the first dielectric layer and the second dielectric layer;
forming a third dielectric layer, a fourth dielectric layer, and a second etch stop layer over the first capacitor, wherein the second etch stop layer separates the third dielectric layer and the fourth dielectric layer, and wherein the fourth dielectric layer is over the third dielectric layer; and
concurrently forming a third via in the third dielectric layer and coupled to the first wire, a second wire in the fourth dielectric layer and coupled to the third via, a fourth via in the third dielectric layer and coupled to the first capacitor, a third wire in the fourth dielectric layer coupled to the fourth via, and a second extend via extending through the third dielectric layer, the second etch stop layer, and the fourth dielectric layer to contact the first extend via and to reach the top surface of the fourth dielectric layer.
10 . The method of claim 9 , wherein the first capacitor is spaced from the first extended via or the second extended via by a distance of less than . 5 micrometers.
11 . The method of claim 7 , wherein the first wire has a first width and the first extended via has a second width that is less than the first width.
12 . The method of claim 7 , further comprising:
forming first plugs within the first via opening and the second via opening before removing portions of the second dielectric layer surrounding the first via opening; and
forming a masking layer overlying the second dielectric layer, wherein the masking layer is patterned to expose a first plug in the first via opening and to cover a second plug in the second via opening.
13 . The method of claim 7 , further comprising forming a barrier layer within the second via opening before depositing the conductive material within the second via opening.
14 . A method of forming an integrated chip, comprising:
forming a first dielectric layer corresponding to a first via level, a second dielectric layer corresponding to a first wire level, and a first etch stop layer separating the first dielectric layer and the second dielectric layer over a substrate, wherein the second dielectric layer is over the first dielectric layer, and wherein the first dielectric layer, the second dielectric layer, and the first etch stop layer are over a first wire and a second wire;
forming a first via opening over the first wire, wherein the first via opening extends both from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer and through the first wire level and into the first via level;
forming a second via opening over the second wire, wherein the second via opening extends both from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer and through the first wire level and into the first via level;;
filling the first and second via openings respectively with a first dielectric plug and a second dielectric plug;
forming a masking layer over the second dielectric layer;
patterning the masking layer to expose the first dielectric plug, wherein the second dielectric plug remains covered after the patterning;
performing an etch, removing portions of the first dielectric plug and the second dielectric layer surrounding the first via opening to form a first wire opening in the second dielectric layer;
removing remaining portions of the first dielectric plug, the second dielectric plug, and the masking layer;
depositing a conductive material in the first via opening, the second via opening, and the first wire opening; and
removing portions of the conductive material above the second dielectric layer, exposing the second dielectric layer, and resulting in a first via remaining in the first dielectric layer, an overlying wire remaining in the second dielectric layer, and a first extended via extending from the top surface of the second dielectric layer to the bottom surface of the first dielectric layer.
15 . The method of claim 14 , wherein the first extended via has a height greater than a combined height of the first via and the overlying wire.
16 . The method of claim 14 , further comprising forming a capacitor on the first wire before forming the first dielectric layer and the second dielectric layer, wherein the first via opening exposes a top electrode of the capacitor and wherein the second via opening extends through the first dielectric layer and the second dielectric layer.
17 . The method of claim 16 , further comprising forming a second extended via before forming the capacitor, wherein the second via opening exposes a top surface of the second extended via, and wherein the second via opening has a height greater than a height of the first via opening.
18 . The method of claim 14 , wherein the first via opening and the second via opening are concurrently etched into the first wire level.
19 . The method of claim 14 , wherein the first via opening is etched into the first via level and the first wire level before the second via opening is etched into the first via level and the first wire level.
20 . The method of claim 14 , wherein the first via extends from a bottom surface of the overlying wire to the first wire and wherein the first extended via extends from a top surface of the overlying wire to the second wire.