Semiconductor package
A semiconductor package includes a package substrate, a semiconductor chip on the package substrate and having a first surface facing the package substrate and a second surface, opposite to the first surface, an encapsulant disposed on the package substrate and on a side surface of the semiconductor chip, a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip, a bonding enhancing layer on the second surface of the semiconductor chip, a thermal interface material layer on the bonding enhancing layer and in a gap between the bonding enhancing layer and the heat dissipation member, wherein the thermal interface material layer includes liquid metal, and a porous barrier structure formed of a metal material and surrounding the bonding enhancing layer and the thermal interface material layer.
1 . A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate and having a first surface facing the package substrate and a second surface, opposite to the first surface;
an encapsulant on the package substrate and on a side surface of the semiconductor chip;
a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip;
a bonding enhancing layer on the second surface of the semiconductor chip;
a thermal interface material layer on the bonding enhancing layer and in a gap between the bonding enhancing layer and the heat dissipation member, wherein the thermal interface material layer comprises a liquid metal; and
a porous barrier structure on side surfaces of the bonding enhancing layer and the thermal interface material layer,
wherein the porous barrier structure is formed of a metal material and surrounds side surfaces of the bonding enhancing layer and the thermal interface material layer.
2 . The semiconductor package of claim 1 , wherein the liquid metal comprises an alloy including gallium, indium, and tin.
3 . The semiconductor package of claim 2 , wherein the bonding enhancing layer comprises at least one of gallium, tin, and copper.
4 . The semiconductor package of claim 1 , wherein the porous barrier structure comprises at least one of copper and nickel.
5 . The semiconductor package of claim 1 , further comprising an adhesive layer between the bonding enhancing layer and the semiconductor chip,
wherein the adhesive layer comprises at least one of gold, platinum, and iridium.
6 . The semiconductor package of claim 1 , wherein the bonding enhancing layer is on opposing sides of the thermal interface material layer.
7 . The semiconductor package of claim 1 , wherein the porous barrier structure is a porous structure having air permeability.
8 . A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate;
a bonding enhancing layer on an upper portion of the semiconductor chip;
a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip;
a thermal interface material layer on the bonding enhancing layer and in a gap between the semiconductor chip and the heat dissipation member, wherein the thermal interface material layer comprises a liquid metal; and
a porous barrier structure on side surfaces of the bonding enhancing layer and the thermal interface material layer, wherein the porous barrier structure comprises a metal material and air permeable pores and surrounds the side surfaces of the bonding enhancing layer and the thermal interface material layer,
wherein the thermal interface material layer does not extend into the air permeable pores of the porous barrier structure.
9 . The semiconductor package of claim 8 , wherein the bonding enhancing layer contacts an upper surface of the semiconductor chip.
10 . The semiconductor package of claim 8 , further comprising an encapsulant on the package substrate and on a side surface of the semiconductor chip.
11 . The semiconductor package of claim 10 , wherein the encapsulant is on an upper surface of the semiconductor chip.
12 . The semiconductor package of claim 11 , wherein the bonding enhancing layer contacts an upper surface of the encapsulant.
13 . The semiconductor package of claim 8 , wherein
the semiconductor chip comprises a plurality of semiconductor chips, and
upper surfaces of each of the plurality of semiconductor chips are at substantially a same level.
14 . A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate;
a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip;
a bonding enhancing layer on the semiconductor chip;
a thermal interface material layer in a gap between the semiconductor chip and the bonding enhancing layer, the thermal interface material layer comprising a liquid metal; and
a porous barrier structure comprising a metal material on side surfaces of the bonding enhancing layer and the thermal interface material layer,
wherein the porous barrier structure surrounds the side surfaces of the bonding enhancing layer and the thermal interface material layer.
15 . The semiconductor package of claim 14 , further comprising an encapsulant on the package substrate and on a side surface of the semiconductor chip.
16 . The semiconductor package of claim 14 , wherein the porous barrier structure is on a side surface of the semiconductor chip.
17 . The semiconductor package of claim 14 , wherein
the porous barrier structure comprises at least one of copper and nickel, and
the bonding enhancing layer comprises at least one of gallium, tin, and copper.
18 . The semiconductor package of claim 17 , further comprising a coating on a surface of the porous barrier structure comprising at least one of gallium, indium, and tin.
19 . The semiconductor package of claim 14 , further comprising an adhesive layer between the bonding enhancing layer and the semiconductor chip,
wherein the adhesive layer comprises at least one of gold, platinum, and iridium.
20 . The semiconductor package of claim 19 , further comprising a barrier layer between the bonding enhancing layer and the thermal interface material layer,
wherein the barrier layer includes at least one of stainless steel, gold, platinum, and nickel.