RFSOI semiconductor structures including an electromagnetic shield layer and methods of manufacturing the same
A semiconductor may include a handle substrate, a semiconductor material layer on which semiconductor devices, metal interconnect structures, dielectric material layers, and an inductor structure are located, and a patterned magnetic shielding layer including at least one portion of a ferromagnetic material having relative permeability of at least 20 and disposed between the semiconductor material layer and the handle substrate and reducing electromagnetic coupling between the inductor structure and the handle substrate.
1 . A semiconductor structure comprising:
a handle substrate;
a patterned magnetic shielding layer comprising at least one portion of a ferromagnetic material having relative permeability of at least 20 and located over the handle substrate;
a semiconductor material layer overlying the patterned magnetic shielding layer;
semiconductor devices located on the semiconductor material layer;
metal interconnect structures embedded within dielectric material layers and electrically connected to the semiconductor devices;
an inductor structure embedded within the dielectric material layers; and
at least one insulating layer embedding the patterned magnetic shielding layer and located between the handle substrate and the semiconductor material layer.
2 . The semiconductor structure of claim 1 , wherein the at least one insulating layer comprises:
a first insulating layer underlying the semiconductor material layer and comprising a first insulating material; and
a second insulating layer underlying the first insulating layer and comprising a second insulating material that is bonded to the first insulating material.
3 . The semiconductor structure of claim 2 , wherein:
the first insulating material comprises a first silicon oxide material; and
the second insulating material comprises a second silicon oxide material.
4 . The semiconductor structure of claim 2 , wherein the patterned magnetic shielding layer is in contact with the first insulating layer and with the second insulating layer.
5 . The semiconductor structure of claim 4 , wherein:
the patterned magnetic shielding layer comprises first horizontal surfaces that are proximal to the semiconductor material layer and second horizontal surfaces that are proximal to the handle substrate and vertically spaced from the first horizontal surfaces by a thickness of the patterned magnetic shielding layer; and
the first horizontal surfaces are located within a same horizontal plane as bonding interfaces between the first insulating layer and the second insulating layer.
6 . The semiconductor structure of claim 1 , further comprising a radio-frequency antenna overlying the dielectric material layers and electrically coupled to the inductor structure, a subset of the metal interconnect structures, and a subset of the semiconductor devices.
7 . The semiconductor structure of claim 1 , wherein the patterned magnetic shielding layer comprises a material selected from Fe, Co, Ni, NiFe, CoFe, NiCo, NiCoFe, and CoZrTa.
8 . The semiconductor structure of claim 1 , wherein the handle substrate comprises a single crystalline silicon layer having a direct-current resistivity in a range from 1.0 Ωcm to 3.0×10 4 Ω-cm.
9 . A semiconductor structure comprising:
semiconductor devices located on a first side of a semiconductor material layer;
metal interconnect structures embedded within dielectric material layers and electrically connected to the semiconductor devices;
an inductor structure embedded within the dielectric material layers;
a handle substrate that underlies the semiconductor material layer;
a patterned magnetic shielding layer comprising at least one portion of a ferromagnetic material having relative permeability of at least 20 and located between the semiconductor material layer and the handle substrate; and
at least one insulating layer embedding the patterned magnetic shielding layer and located between the handle substrate and the inductor structure.
10 . The semiconductor structure of claim 9 , wherein the at least one insulating layer comprises:
a first insulating layer overlying the inductor structure and comprising a first insulating material; and
a second insulating layer overlying the first insulating layer and comprising a second insulating material that is bonded to the first insulating material.
11 . The semiconductor structure of claim 10 , wherein:
the first insulating material comprises a first silicon oxide material; and
the second insulating material comprises a second silicon oxide material.
12 . The semiconductor structure of claim 10 , wherein the patterned magnetic shielding layer is in contact with the first insulating layer and with the second insulating layer.
13 . The semiconductor structure of claim 12 , wherein:
the patterned magnetic shielding layer comprises first horizontal surfaces that are proximal to the semiconductor material layer and second horizontal surfaces that are proximal to the handle substrate and vertically spaced from the first horizontal surfaces by a thickness of the patterned magnetic shielding layer; and
the first horizontal surfaces are located within a same horizontal plane as bonding interfaces between the first insulating layer and the second insulating layer.
14 . The semiconductor structure of claim 9 , further comprising:
a radio-frequency antenna underlying the semiconductor material layer; and
a through-substrate via structure electrically connecting the radio-frequency antenna the inductor structure, a subset of the metal interconnect structures, and a subset of the semiconductor devices.
15 . A method of forming a semiconductor structure;
providing a first assembly including a first semiconductor substrate, semiconductor devices located on the first semiconductor substrate, and dielectric material layers embedding metal interconnect structures and an inductor structure and located over the first semiconductor substrate;
forming a first insulating layer comprising a first insulating material on the first assembly;
providing a second assembly including a handle substrate and a second insulating layer comprising a second insulating material, wherein one of the first insulating layer and the second insulating layer embeds a patterned magnetic shielding layer comprising at least one portion of a ferromagnetic material having relative permeability of at least 20;
bonding the second insulating layer to the first insulating layer by thermocompression dielectric-to-dielectric bonding; and
forming a radio-frequency antenna after the second insulating layer is bonded to the first insulating layer such that the radio-frequency antenna is electrically connected to the inductor structure, a subset of the metal interconnect structures, and a subset of the semiconductor devices.
16 . The method of claim 15 , wherein the first assembly is provided by:
forming the semiconductor devices, the metal interconnect structures, the inductor structure, and the dielectric material layers over a first semiconductor substrate;
attaching a carrier substrate to the dielectric material layers; and
thinning the first semiconductor substrate from a backside, wherein a remaining portion of the first semiconductor substrate comprises the semiconductor material layer.
17 . The method of claim 16 , wherein the first insulating layer is formed on a backside of the semiconductor material layer.
18 . The method of claim 15 , wherein the first insulating layer is formed on top of the dielectric material layers and the inductor structure.
19 . The method of claim 18 , further comprising:
thinning the first semiconductor substrate after the second insulating layer is bonded to the first insulating layer, wherein a remaining portion of the first semiconductor substrate comprises a semiconductor material layer; and
forming a through-substrate via structure through the semiconductor material layer, wherein the radio-frequency antenna is electrically connected to the inductor structure through the through-substrate via structure.
20 . The method of claim 15 , wherein the handle substrate comprises a single crystalline silicon layer having direct-current resistivity in a range from 1.0 Ω-cm to 3.0×10 4 Ω-cm, and has a thickness in a range from 100 microns to 2 mm.