Semiconductor structure comprising sub-alignment marks
A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, and the substrate includes a scribe line region. The semiconductor structure also includes a device layer over the substrate. The device layer includes multiple devices, an interconnection structure electrically connected to the devices, and a dielectric layer surrounding the devices and the interconnection structure. Further, the device layer includes a passivation layer over the device layer, and an alignment mark in the passivation layer over the scribe line region. The alignment mark includes two or more sub-alignment marks, the two or more sub-alignment marks are arranged along an extension direction of the scribe line region, and adjacent sub-alignment marks of the two or more sub-alignment marks are spaced apart from each other.
1 . A semiconductor structure, comprising:
a substrate, wherein the substrate comprises a scribe line region;
a device layer over the substrate, wherein the device layer comprises multiple semiconductor devices;
a passivation layer over the device layer; and
an alignment mark in the passivation layer over the scribe line region, wherein
the alignment mark comprises two or more sub-alignment marks,
the two or more sub-alignment marks are arranged on a plane coplanar with a bottom surface of the passivation layer and the scribe line region contains only one single set of the two or more sub-alignment marks that are aligned with each other along an extension direction thereof within the scribe line region,
a projection of each sub-alignment mark on a surface of the substrate has a rectangle shape, wherein a length direction of the rectangle is parallel to the extension direction of the scribe line region, and a length-to-width ratio of the rectangle is in a range between 1 and 2.4, such that process difficulty and complexity, and material peeling are reduced, and
adjacent sub-alignment marks of the two or more sub-alignment marks aligned along the extension direction of the scribe line region are spaced apart from each other having a gap there-between.
2 . The semiconductor structure according to claim 1 , wherein:
a sub-alignment mark of the two or more sub-alignment marks comprises a metal strip.
3 . The semiconductor structure according to claim 1 , wherein:
a minimum gap between the adjacent sub-alignment marks in the extension direction of the scribe line region is approximately 50 μm, to reduce the material peeling at dicing.
4 . The semiconductor structure according to claim 1 , wherein:
a length of the sub-alignment mark in the extension direction of the scribe line region is in a range approximately between 70 μm and 120 μm, and
a width direction of the rectangle is perpendicular to the extension direction of the scribe line region, and
a width of the sub-alignment mark is in a range approximately between 50 μm and 70 μm.
5 . The semiconductor structure according to claim 1 , wherein:
the substrate further comprises a plurality of first regions adjacent to the scribe line region, wherein the scribe line region is located between adjacent first regions of the plurality of first regions.
6 . The semiconductor structure according to claim 5 , further comprising:
a seal ring over a border between the scribe line region and the adjacent first regions.
7 . The semiconductor structure according to claim 6 , wherein:
in a direction perpendicular to a sidewall surface of the seal ring, a distance between each sub-alignment mark and the seal ring is greater than 5 μm.
8 . The semiconductor structure according to claim 1 , wherein:
in a direction perpendicular to a surface of the substrate, a thickness of each sub-alignment mark from the bottom surface of the passivation layer is in a range approximately between 3.3 μm and 4 μm, such that the two or more sub-alignment marks are configured short and spaced, providing uniform stress distribution and reduced local stress.
9 . The semiconductor structure according to claim 1 , wherein:
the alignment mark is configured for back-end-of-line.
10 . A fabrication method of a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a scribe line region;
forming a device layer over the substrate, wherein the device layer comprises multiple semiconductor devices;
forming a passivation layer over the device layer; and
forming an alignment mark in the passivation layer over the scribe line region, wherein
the alignment mark comprises two or more sub-alignment marks,
the two or more sub-alignment marks are arranged on a plane coplanar with a bottom surface of the passivation layer and the scribe line region contains only one single set of the two or more sub-alignment marks that are aligned with each other along an extension direction thereof within the scribe line region,
a projection of each sub-alignment mark on a surface of the substrate has a rectangle shape, wherein a length direction of the rectangle is parallel to the extension direction of the scribe line region, and a length-to-width ratio of the rectangle is in a range between 1 and 2.4, such that process difficulty and complexity, and material peeling are reduced, and
adjacent sub-alignment marks of the two or more sub-alignment marks aligned along the extension direction of the scribe line region are spaced apart from each other having a gap there-between.
11 . The method according to claim 10 , forming the passivation layer and the alignment mark comprises:
forming a lower passivation layer over the device layer;
etching the lower passivation layer over the scribe line region, to from two or more grooves in the lower passivation layer over the scribe line region;
forming the two or more sub-alignment marks in the two or more grooves; and
forming an upper passivation layer on the lower passivation layer and on surfaces of the two or more sub-alignment marks, wherein the upper passivation layer and the lower passivation layer form the passivation layer.
12 . The method according to claim 10 , wherein:
the substrate further comprises a plurality of first regions adjacent to the scribe line region, wherein the scribe line region is located between adjacent first regions of the plurality of first regions.
13 . The method according to claim 12 , further comprising:
performing a dicing process on the scribe line region to form a plurality of mutually independent chips, wherein each chip comprises a first region of the plurality of first regions.
14 . The method according to claim 10 , wherein:
a sub-alignment mark of the two or more sub-alignment marks comprises a metal strip.
15 . The method according to claim 10 , wherein:
a length of the sub-alignment mark is in a range approximately between 70 μm and 120 μm;
a width of the sub-alignment mark is in a range approximately between 50 μm and 70 μm; and
a minimum distance between the adjacent sub-alignment marks in the extension direction of the scribe line region is approximately 50 μm.
16 . The method according to claim 10 , wherein:
in a direction perpendicular to a surface of the substrate, a thickness of the sub-alignment mark is in a range approximately between 3.3 μm and 4 μm.
17 . The method according to claim 10 , further comprising:
forming test keys and metal pads in the passivation layer over the scribe line region.