Semiconductor device quad-flat-no-leads package with trenches for improved soldering and method of making thereof

1 . A quad-flat-no-leads (QFN) packaged semiconductor device having a QFN bottom surface and a plurality of QFN side faces, the QFN packaged semiconductor device comprising:

a die pad within the QFN bottom surface; and

a plurality of I/O terminals spaced apart from the die pad and around a periphery of the QFN bottom surface, each I/O terminal of the plurality of I/O terminals having:

a bottom face extending from an inner end to a peripheral end, and

an exposed side face on a QFN side face of the plurality of QFN side faces and comprising a non-recessed upper portion extending beyond a recessed lower portion of the exposed side face,

wherein the QFN bottom surface includes at least one trench therein, parallel to at least one QFN side face of the plurality of QFN side faces and exposing at least a part of a side face of the inner end of each of the I/O terminals of the plurality of I/O terminals, and

each I/O terminal of the plurality of I/O terminals comprising a buried portion extending beyond the at least one trench towards the die pad and spaced apart therefrom.

2 . The QFN packaged semiconductor device according to claim 1 , wherein the at least one trench comprises a respective trench parallel to each of the QFN side faces of the plurality of QFN side faces.

3 . The QFN packaged semiconductor device according to claim 1 , wherein a depth of the at least one trench is less than a height of the recessed lower portion of the exposed side face.

4 . The QFN packaged semiconductor device according to claim 1 , wherein the buried portion extends from its inner end.

5 . The QFN packaged semiconductor device according to claim 4 , wherein each I/O terminal of the plurality of I/O terminals has a first thickness between its inner end and its peripheral end, and a second thickness, less than the first thickness, in its buried portion.

6 . The QFN packaged semiconductor device according to claim 5 , wherein a depth of the trench is less than a difference between the first thickness and the second thickness.

7 . The QFN packaged semiconductor device according to claim 5 , wherein a depth of the trench is more than a difference between the first thickness and the second thickness, and less than the first thickness.

8 . A method of manufacturing a QFN packaged semiconductor device having a QFN bottom surface and QFN side faces, and comprising a die pad on the QFN bottom surface, and a plurality of I/O terminals spaced apart from the die pad around a periphery of the QFN bottom surface, each having a bottom face extending from an inner end to a peripheral end, and an exposed side face on a one of the QFN side faces, the method comprising:

attaching a die on the die pad;

forming wirebonds between the die and the plurality of I/O terminals;

encapsulating the die and wirebonds;

forming a first trench in the QFN bottom surface, thereby exposing a part of an inner side face of an inner end of each of the plurality of I/O terminals, each I/O terminal of the plurality of I/O terminals comprising a buried portion extending beyond the first trench towards the die pad and spaced apart therefrom;

forming a second trench in the QFN bottom surface, proximate to the peripheral end of each of the plurality of I/O terminals thereby exposing a part of a side face of each of the plurality of I/O terminals; and

singulating the QFN semiconductor device package, thereby exposing a remainder of the side face of each of the I/O terminals,

wherein the second trench is positioned so as to form a recessed lower portion of the side face of each of the I/O terminals.

9 . The method of claim 8 , wherein the first trench and second trench are formed concurrently using a dual-blade.

10 . The method of claim 8 , wherein a depth of the first trench is less than a depth of the second trench.