Strip substrate and semiconductor package including the same
A strip substrate comprises a dielectric layer comprising a unit region and a saw line region, a saw line pattern on the saw line region, a conductive dummy pattern extending from the saw line pattern and toward the unit region, and power/ground patterns on the unit region. The power/ground pattern includes a first lateral surface that extends in a first direction and is proximate to the saw line pattern, a second lateral surface that extends in a second direction and is proximate to the conductive dummy pattern, and a third lateral surface that connects the first lateral surface and the second lateral surface.
1 . A strip substrate, comprising:
a dielectric layer comprising a unit region and a saw line region;
a saw line pattern on the saw line region of the dielectric layer;
a conductive dummy pattern that extends from the saw line pattern and toward the unit region; and
a plurality of power/ground patterns on the unit region,
wherein the conductive dummy pattern is between the plurality of power/ground patterns, and
wherein each of the plurality of power/ground patterns includes:
a first lateral surface that extends in a first direction and is proximate to the saw line pattern;
a second lateral surface that extends in a second direction and is proximate to the conductive dummy pattern, wherein the second direction intersects the first direction; and
a third lateral surface that connects the first lateral surface and the second lateral surface to each other.
2 . The strip substrate of claim 1 , wherein a distance between the third lateral surface and the conductive dummy pattern increases as a distance between the third lateral surface and the saw line pattern decreases.
3 . The strip substrate of claim 1 , wherein the third lateral surface includes a flat surface or a concave surface.
4 . The strip substrate of claim 3 , wherein:
the third lateral surface includes the flat surface, and
an angle between the third lateral surface and one of the first lateral surface and the second lateral surface is in a range of about 120 degrees to about 150 degrees.
5 . The strip substrate of claim 1 , wherein the third lateral surface includes:
a fourth lateral surface connected to the first lateral surface and parallel to the second lateral surface; and
a fifth lateral surface connected to the second lateral surface and the fourth lateral surface and parallel to the first lateral surface,
wherein a distance between the conductive dummy pattern and the fourth lateral surface is greater than a distance between the conductive dummy pattern and the second lateral surface.
6 . The strip substrate of claim 1 , wherein each of the plurality of power/ground patterns include a metal plate pattern.
7 . The strip substrate of claim 1 , wherein:
a distance between the saw line pattern and the first lateral surface of a power/ground pattern from among the plurality of power/ground patterns is in a range of about 50 micrometers to about 150 micrometers, and
a distance between the conductive dummy pattern and the second lateral surface of the power/ground pattern is in a range of about 10 micrometers to about 30 micrometers.
8 . The strip substrate of claim 1 , wherein a distance between the third lateral surface and the conductive dummy pattern is greater than or equal to a distance between the second lateral surface and the conductive dummy pattern.
9 . The strip substrate of claim 1 , further comprising:
a plurality of solder pads on the unit region of the dielectric layer, and wherein the plurality of solder pads are laterally arranged on and connected to the conductive dummy patterns; and
a dielectric protection layer on the dielectric layer, the saw line pattern, and the conductive dummy patterns.
10 . A semiconductor package, comprising:
a package substrate comprising a lateral surface, a top surface, and a bottom surface opposite to the top surface;
a semiconductor chip on the top surface of the package substrate; and
a solder terminal on the bottom surface of the package substrate,
wherein the package substrate includes:
a dielectric layer;
a solder pad between the solder terminal and the dielectric layer;
a conductive dummy pattern on the dielectric layer, wherein the conductive dummy pattern extends from the solder pad toward the lateral surface of the package substrate, and wherein a portion of the conductive dummy pattern is exposed at the lateral surface of the package substrate; and
a plurality of power/ground patterns proximate to the lateral surface and on the dielectric layer,
wherein the conductive dummy pattern is between the plurality of power/ground patterns,
wherein each of the plurality of power/ground patterns includes:
a first part; and
a second part between the first part and the lateral surface of the package substrate,
wherein a first distance between the first part and the conductive dummy pattern in a first direction is constant,
wherein a second distance between the second part and the conductive dummy pattern in a second direction increases as a third distance between the second part and the lateral surface of the package substrate in the first direction decreases, and
wherein the second direction intersects the first direction.
11 . The semiconductor package of claim 10 , wherein the second distance is greater than the first distance.
12 . The semiconductor package of claim 10 , wherein
the first distance is in a range of about 10 micrometers to about 30 micrometers, and
the second distance is greater than or equal to the first distance.
13 . The semiconductor package of claim 10 , wherein the third distance is in a range of about 50 micrometers to about 150 micrometers.
14 . The semiconductor package of claim 10 , wherein:
the first part comprises a first lateral surface,
the second part comprises a second lateral surface, and
an angle between the second lateral surface and the first lateral surface is in a range of about 120 degrees to about 150 degrees.
15 . The semiconductor package of claim 14 , wherein the second lateral surface includes a substantially flat surface or a concave surface.
16 . The semiconductor package of claim 14 , wherein a power/ground pattern from among the plurality of power/ground patterns further includes a third part between the first part and the second part,
wherein the third part has a third lateral surface, and
wherein the third lateral surface is inclined to the first lateral surface and the second lateral surface.
17 . The semiconductor package of claim 10 , wherein the power/ground pattern comprises a metal plate pattern.
18 . A strip substrate, comprising:
a dielectric layer;
a saw line pattern that extends in a first direction on the dielectric layer;
a plurality of metal plate patterns spaced apart from each other in the first direction;
a solder pad on the dielectric layer;
a conductive dummy pattern that extends from the solder pad and between the plurality of metal plate patterns, wherein the conductive dummy pattern is connected to the saw line pattern; and
a dielectric protection layer on the dielectric layer, the saw line pattern, the plurality of metal plate patterns, and the conductive dummy pattern,
wherein a first distance between the plurality of metal plate patterns and the conductive dummy pattern is in a range of about 10 micrometers to about 30 micrometers,
wherein a second distance between the plurality of metal plate patterns and the saw line pattern is in a range of about 50 micrometers to about 150 micrometers, and
wherein each of the plurality of metal plate patterns comprises a chamfer shape at a corner proximate to an intersection of the saw line pattern and the conductive dummy pattern.
19 . The strip substrate of claim 18 , wherein each of the plurality of metal plate patterns includes:
a first lateral surface that extends along the saw line pattern;
a second lateral surface that extends along the conductive dummy pattern; and
a third lateral surface inclined to each of the first lateral surface and the second lateral surface.
20 . The strip substrate of claim 19 , wherein the third lateral surface includes a substantially flat surface or a concave surface.