IP Library › Granted Patent US 12685203
Granted Patent B2
US 12685203 · App. 18/763,481 · Granted Jul 14, 2026

Bump integration with redistribution layer

Inventors: Ting-Li Yang (Tainan City, TW); Po-Hao Tsai (Zhongli City, TW); Ching-Wen Hsiao (Hsinchu, TW); Hong-Seng Shue (Zhubei City, TW); Ming-Da Cheng (Taoyuan City, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10W72/20H10W20/089H10W20/42H10W20/435H10W20/496H10W72/01208H10W72/221
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Quick Facts
Patent No.
US 12685203
App. No.
18/763,481
Granted
Jul 14, 2026
Kind
B2
Abstract

A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

Claims (49)

1 . A semiconductor device comprising:

a substrate comprising a device region;

an interconnect structure over the substrate and electrically coupled to the device region;

a first passivation layer over the interconnect structure;

a conductive pad over the first passivation layer and electrically coupled to the interconnect structure;

a first via in the first passivation layer under the conductive pad, wherein the first via contacts the conductive pad and extends from an upper surface of the first passivation layer distal from the substrate to a conductive feature of the interconnect structure;

a second via in the first passivation layer under the conductive pad, wherein the second via contacts the conductive pad and extends into, but not through, the first passivation layer;

a second passivation layer over the conductive pad and the first passivation layer, wherein the second passivation layer is conformal and extends along sidewalls of the conductive pad and an upper surface of the conductive pad;

a dielectric layer over the second passivation layer, wherein the dielectric layer extends further from the substrate than the conductive pad;

a bump via in the dielectric layer, wherein the bump via extends from an upper surface of the dielectric layer distal from the substrate to the conductive pad, wherein a portion of the dielectric layer is disposed laterally between the bump via and the second passivation layer, and separates the bump via from the second passivation layer; and

a conductive bump on the bump via.

2 . The semiconductor device of claim 1 , wherein a width of the bump via changes continuously as the bump via extends toward the conductive pad.

3 . The semiconductor device of claim 1 , further comprising a solder region on the conductive bump.

4 . The semiconductor device of claim 1 , wherein the bump via and the conductive bump comprise a same electrically conductive material.

5 . The semiconductor device of claim 1 , wherein the first via is centered with respect to the conductive pad, and the second via is off-center with respect to the conductive pad.

6 . The semiconductor device of claim 1 , further comprising a metal-insulator-metal (MIM) capacitor embedded in the first passivation layer, wherein the MIM capacitor comprises an upper metal layer, a lower metal layer, and a dielectric material in-between, wherein the second via contacts the MIM capacitor.

7 . The semiconductor device of claim 6 , wherein the second via contacts the upper metal layer of the MIM capacitor.

8 . The semiconductor device of claim 6 , wherein the second via extends through an opening in the upper metal layer of the MIM capacitor without contacting the upper metal layer, wherein the second via extends through the dielectric material of the MIM capacitor and contacts the lower metal layer of the MIM capacitor.

9 . A semiconductor device comprising:

a substrate;

an interconnect structure over the substrate;

a first passivation layer over the interconnect structure;

a conductive pad over the first passivation layer;

a first via in the first passivation layer under the conductive pad, wherein the first via electrically couples the conductive pad to the interconnect structure;

a second via in the first passivation layer under the conductive pad, wherein the conductive pad contacts the first via and the second via, wherein the first via extends closer to the substrate than the second via;

a second passivation layer over the conductive pad and the first passivation layer, wherein the second passivation layer is conformal and extends along sidewalls of the conductive pad and an upper surface of the conductive pad distal from the substrate;

a dielectric layer over the second passivation layer, wherein the upper surface of the conductive pad is closer to the substrate than an upper surface of the dielectric layer distal from the substrate;

a bump via in the dielectric layer, wherein the bump via extends from the upper surface of the dielectric layer to the conductive pad, wherein a portion of the dielectric layer is disposed laterally between the bump via and the second passivation layer and separates the bump via from the second passivation layer; and

a conductive bump on the bump via.

10 . The semiconductor device of claim 9 , further comprising a metal-insulator-metal (MIM) capacitor embedded in the first passivation layer, wherein the second via extends from the conductive pad to the MIM capacitor.

11 . The semiconductor device of claim 10 , wherein the first via extends from the conductive pad to a conductive feature of the interconnect structure.

12 . A semiconductor device comprising:

a substrate;

an interconnect structure over the substrate;

a first passivation layer over the interconnect structure;

a conductive pad over the first passivation layer;

a first via and a second via that are disposed in the first passivation layer under the conductive pad, wherein the conductive pad contacts the first via and the second via, wherein the first via extends closer to the substrate than the second via;

a second passivation layer over the conductive pad and the first passivation layer, wherein the second passivation layer is conformal and extends along sidewalls of the conductive pad and an upper surface of the conductive pad distal from the substrate;

a dielectric layer over the second passivation layer, wherein the dielectric layer extends further from the substrate than the conductive pad;

a conductive bump over the dielectric layer; and

a bump via in the dielectric layer, wherein the bump via extends from the conductive bump to the conductive pad.

13 . The semiconductor device of claim 12 , wherein a width of the bump via, measured between opposing sidewalls of the bump via at an upper surface of the conductive pad distal from the substrate, is smaller than a distance measured at the upper surface of the conductive pad between opposing sidewalls of the second passivation layer facing the bump via.

14 . The semiconductor device of claim 13 , wherein the opposing sidewalls of the second passivation layer are spaced apart from the bump via by a portion of the dielectric layer interposed between the bump via and the second passivation layer.

15 . The semiconductor device of claim 12 , wherein the first via extends from the conductive pad to a conductive feature of the interconnect structure.

16 . The semiconductor device of claim 15 , further comprising a metal-insulator-metal (MIM) capacitor embedded in the first passivation layer, wherein the second via extends from the conductive pad to the MIM capacitor.

17 . The semiconductor device of claim 16 , wherein the MIM capacitor comprises an upper metal layer, a lower metal layer, and a dielectric material in-between, wherein the lower metal layer is between the substrate and the upper metal layer.

18 . The semiconductor device of claim 17 , wherein the second via is in contact with the upper metal layer.

19 . The semiconductor device of claim 17 , wherein the second via extends through an opening in the upper metal layer without contacting the upper metal layer, wherein the second via is in contact with the lower metal layer.

20 . The semiconductor device of claim 12 , wherein the conductive bump and the bump via comprise a same conductive material.