Delamination/cracking improvement at solder joints in microelectronics package
The present disclosure relates to a microelectronics package with significantly reduced delamination/cracking at solder joints, and a process for making the same. The disclosed microelectronics package includes a carrier, a solder joint region over the carrier, a top intermetallic (IMC) layer over the solder joint region, and a device die over the top IMC layer. Herein, the device die includes a substrate, an active device over the substrate, a top barrier layer underneath the substrate, and a backside metal layer vertically between the top IMC layer and the top barrier layer. The backside metal layer is formed of gold (Au) with a thickness at least 0.5 μm. The top IMC layer comprises gold nickel tin (AuNiSn) or gold platinum tin (AuPtSn), and the solder joint region comprises an Au-rich gold-tin (Au 5 Sn) and gold-tin (AuSn) eutectic mixture.
1 . A microelectronics package comprising:
a carrier;
a solder joint region formed over the carrier;
a top intermetallic (IMC) layer formed over the solder joint region; and
a device die formed over the top IMC layer, wherein:
the device die includes a substrate, an active device formed over the substrate, a top barrier layer formed underneath the substrate, and a backside metal layer formed vertically between the top IMC layer and the top barrier layer;
the backside metal layer is formed of copper (Cu) and has a thickness of at least 0.5 μm;
the solder joint region comprises an Au-rich gold-tin (AusSn) and gold-tin (AuSn) eutectic mixture; and
the top IMC layer comprises copper nickel tin (CuNiSn) and gold nickel tin (AuNiSn), or comprises copper platinum tin (CuPtSn) and gold platinum tin AuPtSn.
2 . The microelectronics package of claim 1 wherein the backside metal layer has a thickness between 0.5 μm and 10 μm.
3 . The microelectronics package of claim 1 wherein the top barrier layer is formed underneath the substrate via an adhesion layer.
4 . The microelectronics package of claim 1 wherein the top barrier layer is formed directly underneath the substrate.
5 . The microelectronics package of claim 1 wherein:
the active device is one of a group consisting of a Gallium Nitride (GaN) device, a silicon (Si) device, and a Gallium Arsenide (GaAs) device; and
the substrate is formed of one of a group consisting of silicon carbon (SiC), Si, GaN, Sapphire, and GaAs.
6 . The microelectronics package of claim 1 further comprising a bottom IMC layer vertically between the carrier and the solder joint region, wherein:
the carrier includes a base plate and a bottom barrier over the base plate; and
the bottom IMC layer is formed over the bottom barrier of the carrier.
7 . The microelectronics package of claim 6 wherein:
the bottom IMC layer comprises AuNiSn;
the bottom barrier is formed of nickel (Ni); and
the base plate comprises Cu.
8 . A microelectronics package comprising:
a carrier;
a solder joint region formed over the carrier;
a top intermetallic (IMC) layer formed over the solder joint region; and
a device die formed over the top IMC layer, wherein:
the device die includes a substrate, an active device formed over the substrate, a top barrier layer formed underneath the substrate, and a backside metal layer formed vertically between the top IMC layer and the top barrier layer;
the backside metal layer is formed of gold (Au);
the top IMC layer comprises gold platinum tin (AuPtSn); and
the solder joint region comprises an Au-rich gold-tin (AusSn) and gold-tin (AuSn) eutectic mixture.
9 . The microelectronics package of claim 8 wherein the backside metal layer has a thickness between 0.5 μm and 10 μm.
10 . The microelectronics package of claim 8 wherein the top barrier layer is formed underneath the substrate via an adhesion layer.
11 . The microelectronics package of claim 8 wherein the top barrier layer is formed directly underneath the substrate.
12 . The microelectronics package of claim 8 wherein:
the active device is one of a group consisting of a Gallium Nitride (GaN) device, a silicon (Si) device, and a Gallium Arsenide (GaAs) device; and
the substrate is formed of one of a group consisting of silicon carbon (SiC), Si, GaN, Sapphire, and GaAs.
13 . The microelectronics package of claim 8 further comprising a bottom IMC layer vertically between the carrier and the solder joint region, wherein:
the carrier includes a base plate and a bottom barrier over the base plate; and
the bottom IMC layer is formed over the bottom barrier of the carrier.
14 . The microelectronics package of claim 13 wherein:
the bottom IMC layer comprises AuNiSn;
the bottom barrier is formed of nickel (Ni); and
the base plate comprises Cu.