IP Library Granted Patent US 12685209
Granted Patent B2
US 12685209 · App. 18/052,246 · Granted Jul 14, 2026

Semiconductor package with a cured electrically conductive paste interconnect and method for producing the same

Inventors: Chi Ho Leung (Nijmegen, NL); Shun Tik Yeung (Nijmegen, NL); King Man Tai (Nijmegen, NL); Ka Shing Martin Li (Nijmegen, NL)
Assignee: Nexperia B.V.
H10W74/121H10W70/421H10W74/01H10W74/111H10W74/47H10W72/016H10W72/07631H10W72/625H10W72/652H10W72/653H10W90/761
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Quick Facts
Patent No.
US 12685209
App. No.
18/052,246
Granted
Jul 14, 2026
Kind
B2
Abstract

A method for producing a semiconductor package includes providing a lead frame and a bond pad with a space therebetween. The frame is provided with a die bonded thereon and a die pad. The die, the pad, a part of the frame, a part of the bond pad and the space between the frame and the bond pad are encapsulated. Part of the first encapsulation is removed to create a cavity having a bottom surface including an exposed surface of the die, an exposed surface of the pad, an exposed surface of the bond pad and a connecting region between the exposed surface of the pad and the bond pad. The cavity is partly filled with an electrically conductive paste. The electrically conductive paste is cured to obtain an interconnect between the die pad and the bond pad. The interconnect is encapsulated.

Claims (29)

1 . A method for producing a semiconductor package, comprising the steps of:

providing a lead frame and a bond pad with a space therebetween wherein a bottom surface of bond pad comprises an external terminal for mounting to a printed circuit board at a bottom surface of the semiconductor package;

wherein the lead frame is provided with a die bonded thereon and the die is provided with a die pad;

wherein the die, the die pad, a part of the lead frame, a part of the bond pad and the space between the lead frame and the bond pad are encapsulated by a first encapsulation, and wherein the encapsulation encapsulates a top surface of the bond pad opposite and directly above the bottom surface of the bond pad comprising the external terminal;

removing part of the first encapsulation to create a cavity having a bottom surface comprising an exposed surface of the die comprising an exposed surface of the die pad, an exposed surface of the bond pad and a connecting region between the exposed surface of the die pad and the exposed surface of the bond pad;

partly filling the cavity with an electrically conductive paste to cover the bottom surface of the cavity;

curing the electrically conductive paste to obtain an interconnect consisting of the cured conductive paste between the die pad and the bond pad; and

encapsulating the interconnect by providing a second encapsulation over the interconnect.

2 . The method according to claim 1 , wherein the removing part of the first encapsulation is performed by laser or computer numerical control machining.

3 . The method according to claim 1 , wherein the electrically conductive paste is an epoxy resin comprising Ag or a Cu sintering paste.

4 . The method according to claim 1 , wherein the first and the second encapsulations comprise electrically non-conductive materials.

5 . The method according to claim 1 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of the same composition.

6 . The method according to claim 1 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of different composition.

7 . The method according to claim 2 , wherein the electrically conductive paste is an epoxy resin comprising Ag or a Cu sintering paste.

8 . The method according to claim 2 , wherein the first and the second encapsulations comprise electrically non-conductive materials.

9 . The method according to claim 2 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of the same composition.

10 . The method according to claim 2 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of different composition.

11 . A semiconductor package comprising

a lead frame and a bond pad with a space therebetween, wherein a bottom surface of bond pad comprises an external terminal for mounting to a printed circuit board at a bottom surface of the semiconductor package;

wherein the lead frame is provided with a die bonded thereon and the die is provided with a die pad;

an interconnect between the die pad and the bond pad consisting of a cured electrically conductive paste; and

an encapsulation encapsulating the interconnect, the die, the die pad, a part of the lead frame, a part of the bond pad and the space between the lead frame and the bond pad, wherein the encapsulation encapsulates a top surface of the bond pad opposite and directly above the bottom surface of the bond pad comprising the external terminal.

12 . The semiconductor package according to claim 11 , wherein the electrically conductive paste is an epoxy resin comprising Ag or a Cu sintering paste.

13 . The semiconductor package according to claim 12 , wherein the encapsulation comprises a first encapsulation covering the die, the die pad, the part of the lead frame, the part of the bond pad and the space between the lead frame and the bond pad and a second encapsulation covering the interconnect.

14 . The semiconductor package according to claim 13 , wherein the first and the second encapsulations comprise electrically non-conductive materials.

15 . The semiconductor package according to claim 13 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of the same composition.

16 . The semiconductor package according to claim 13 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of different composition.

17 . The semiconductor package according to claim 14 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of the same composition.

18 . The semiconductor package according to claim 14 , wherein the first encapsulation comprises a first epoxy molding compound and the second encapsulation comprises a second epoxy molding compound, and wherein the first epoxy molding compound and the second epoxy molding compound are of different composition.