Semiconductor package and method for manufacturing the semiconductor package
A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures.
1 . A semiconductor package comprising:
a substrate;
a circuit layer disposed on a lower surface of the substrate, the circuit layer comprising an interconnection structure;
a first redistribution structure disposed adjacent to the circuit layer on the lower surface of the substrate, the first redistribution structure comprising a first redistribution layer;
a connection structure comprising:
a first connection via electrically connected to the first redistribution layer;
a second connection via electrically connected to the interconnection structure; and
a connection interconnection disposed below the first connection via and the second connection via and interconnecting the first connection via and the second connection via;
a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer;
a first vertical connection structure disposed on a lower surface of the circuit layer;
a second vertical connection structure disposed on a lower surface of the connection structure; and
a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures, the second redistribution structure comprising a second redistribution layer.
2 . The semiconductor package of claim 1 , wherein the second vertical connection structure extends in a first direction, parallel to a side surface of the semiconductor chip.
3 . The semiconductor package of claim 1 , wherein the connection structure further comprises a connection pad disposed on an upper surface of the second connection via, and
wherein the connection pad is connected to the interconnection structure and the second connection via.
4 . The semiconductor package of claim 1 , wherein the semiconductor chip further comprises a connection pad disposed on an upper surface of the semiconductor chip,
wherein the first redistribution structure comprises first redistribution layers, and
wherein the semiconductor package further comprises a bump disposed between a lower surface of a lowermost first redistribution layer among the first redistribution layers and an upper surface of the connection pad.
5 . The semiconductor package of claim 1 , wherein the semiconductor chip further comprises a connection pad disposed on an upper surface of the semiconductor chip,
wherein the first redistribution structure comprises first redistribution layers,
wherein the semiconductor package further comprises a first bonding pad disposed on a lower surface of a lowermost first redistribution layer among the first redistribution layers and a second bonding pad disposed on an upper surface of the connection pad, and
wherein a lower surface of the first bonding pad contacts an upper surface of the second bonding pad.
6 . The semiconductor package of claim 1 , wherein the second redistribution structure further comprises a second redistribution via connected to the second redistribution layer, and
wherein a lower surface of the semiconductor chip contacts an upper surface of the second redistribution via.
7 . The semiconductor package of claim 1 , wherein the semiconductor package further comprises an encapsulant encapsulating at least a portion of each of the first and second vertical connection structures, the semiconductor chip, and the connection structure.
8 . The semiconductor package of claim 1 , wherein a distance between the semiconductor chip and the second vertical connection structure is in a range of about 0.001 mm to about 1 mm.
9 . The semiconductor package of claim 1 , wherein the connection structure further comprises a connection insulating layer covering the connection interconnection, and
wherein a distance between the semiconductor chip and the connection insulating layer is in a range of about 0.001 mm to about 1 mm.
10 . The semiconductor package of claim 1 , wherein an area of the semiconductor chip is in a range of about 5% to about 99% of an area of the substrate, and
wherein an area of the second vertical connection structure is in a range of about 0.10% to about 50% of the area of the substrate.
11 . The semiconductor package of claim 1 , wherein a width of the second vertical connection structure is in a range of about 0.001 mm to about 1 mm, and
wherein a height of the second vertical connection structure is in a range of about 0.001 mm to about 1 mm.
12 . The semiconductor package of claim 1 , wherein a height of the substrate is in a range of about 0.005 mm to about 1 mm, and
wherein a sum of a height of the circuit layer, a height of the first vertical connection structure, and a height of the second redistribution structure is in a range of about 0.01 mm to about 1 mm.
13 . The semiconductor package of claim 1 , wherein a height of the first redistribution structure is greater than a height of the circuit layer.
14 . A semiconductor package comprising:
a substrate;
a circuit layer disposed on a lower surface of the substrate, the circuit layer comprising an interconnection structure and an interlayer insulating layer surrounding the interconnection structure;
a first redistribution structure disposed adjacent to the circuit layer on the lower surface of the substrate, the first redistribution structure comprising a first redistribution layer and a first redistribution insulating layer surrounding the first redistribution layer;
a connection insulating layer having an upper surface contacting a lower surface of the first redistribution insulating layer and a lower surface of the interlayer insulating layer;
a semiconductor chip disposed below the first redistribution structure and electrically connected to the first redistribution layer;
an underfill layer disposed between the first redistribution structure and the semiconductor chip;
a first vertical connection structure disposed on a lower surface of the circuit layer;
a second vertical connection structure disposed on a lower surface of the connection insulating layer; and
a second redistribution structure disposed below the first vertical connection structure and the second vertical connection structure, the second redistribution structure comprising a second redistribution layer,
wherein the interlayer insulating layer and the first redistribution insulating layer comprise different materials.
15 . The semiconductor package of claim 14 , wherein the interlayer insulating layer comprises silicon oxide, and
wherein the first redistribution insulating layer comprises a photosensitive insulating material.
16 . The semiconductor package of claim 14 , wherein the upper surface of the connection insulating layer and a side surface of the connection insulating layer form a right angle.
17 . The semiconductor package of claim 14 , wherein the upper surface of the connection insulating layer and a side surface of the connection insulating layer form an obtuse angle.
18 . A semiconductor package, comprising:
a substrate;
a circuit layer disposed on a lower surface of the substrate, the circuit layer comprising an interconnection structure;
a first redistribution structure disposed adjacent to the circuit layer on the lower surface of the substrate, the first redistribution structure comprising a first redistribution layer;
a connection structure comprising:
a connection interconnection electrically connected to the interconnection structure and the first redistribution layer; and
a connection insulating layer covering the connection interconnection;
a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer;
a first vertical connection structure disposed on a lower surface of the circuit layer;
a second vertical connection structure disposed on a lower surface of the connection structure; and
a second redistribution structure disposed below the first and second vertical connection structures, the second redistribution structure comprising a second redistribution layer,
wherein the second vertical connection structure contacts the connection insulating layer, and is electrically connected to the second redistribution layer.
19 . The semiconductor package of claim 18 , wherein the second redistribution structure further comprises second redistribution vias connecting the second redistribution layer and the second vertical connection structure.
20 . The semiconductor package of claim 18 , wherein a height of the second vertical connection structure is smaller than a height of the first vertical connection structure.