Composite IC die package including IC die directly bonded to front and back sides of an interposer

1 . An integrated circuit (IC) die package comprising:

an interposer with one or more first through vias, wherein routing metallization is on a first side of the interposer;

a first IC die, wherein a back side of the first IC die comprises a first metal feature coupled to a second through via within the first IC die, and wherein the first metal feature is in direct contact with a second metal feature on a second side of the interposer;

an insulator over the first IC die, in contact with an edge of the first IC die, and over a portion of the interposer extending beyond the edge of the first IC die;

a plurality of metal redistribution layer (RDL) features over the insulator and electrically coupled to corresponding ones of a plurality of third metal features on a front side of the first IC die, wherein the RDL features and the first through vias terminate at first-level interconnect interfaces; and

a second IC die electrically coupled to at least one of the first through vias, wherein a front side of the second IC die comprises fourth metal features in direct contact with fifth metal features of the routing metallization.

2 . The IC die package of claim 1 , wherein:

the first metal feature is embedded within a first dielectric material on the back side of the first IC die;

the second metal feature is embedded within a second dielectric material on the second side of the interposer; and

the first dielectric material that is around the first metal feature is in direct contact with the second dielectric material that is around the second metal feature, and wherein an interdiffused metallurgical bond joins the first metal feature to the second metal feature.

3 . The IC die package of claim 1 , wherein the routing metallization is embedded within an inorganic dielectric material comprising at least two of silicon, oxygen, or nitrogen.

4 . The IC die package of claim 1 , wherein the second metal feature is adjacent to an inorganic dielectric material comprising at least two of silicon, oxygen, or nitrogen.

5 . The IC die package of claim 1 , wherein the RDL features are embedded within an organic dielectric material.

6 . The IC die package of claim 1 , further comprising an organic epoxy adjacent to a side of the second IC die.

7 . The IC die package of claim 1 , wherein:

a first of the first through vias are coupled to a corresponding one of a plurality of conductive pillars on the second side of the interposer, the conductive pillars extending through the insulator beyond the edge of the first IC die;

the first IC die is adjacent to, and between, two of the plurality of conductive pillars; and

the RDL features terminate at first-level interconnect (FLI) interfaces.

8 . The IC die package of claim 7 , wherein:

the first IC die is one of a plurality of first IC die; and

the RDL features electrically interconnect the plurality of first IC die.

9 . The IC die package of claim 8 , wherein:

the second IC die is one of a plurality of second IC die; and

the routing metallization electrically interconnects the plurality of second IC die, and electrically couples each of the plurality of second IC die to one or more of the first through vias.

10 . The IC die package of claim 7 , further comprising solder features in contact with the FLI interfaces.

11 . The IC die package of claim 7 , wherein the plurality of conductive pillars have a height at least equal to a thickness of the first IC die.

12 . The IC die package of claim 11 , wherein the conductive pillars terminate at the FLI interfaces.

13 . The IC die package of claim 1 , wherein the interposer comprises a substrate of a thickness and the first through vias are through substrate vias extending through the thickness of the substrate.

14 . The IC die package of claim 13 , wherein the substrate is a crystalline material comprising silicon.

15 . The IC die package of claim 13 , wherein the substrate is glass.

16 . A system comprising:

a host component;

an interposer with one or more first through vias, wherein routing metallization is on a first side of the interposer;

a first IC die, wherein a back side of the first IC die comprises a first metal feature coupled to a second through via within the first IC die, and wherein the first metal feature is in direct contact with a second metal feature on a second side of the interposer;

an insulator over the first IC die, in contact with an edge of the first IC die;

a plurality of metal redistribution layer (RDL) features over the insulator and electrically coupled to corresponding ones of a plurality of third metal features on a front side of the first IC die, wherein the RDL features and the first through vias terminate at first-level interconnect (FLI) interfaces;

solder features interconnecting the FLI interfaces to the host component; and

a second IC die electrically coupled to at least one of the first through vias, wherein a front side of the second IC die comprises fourth metal features in direct contact with fifth metal features of the routing metallization.

17 . The system of claim 16 , further comprising:

a power supply coupled to the host component to power the first and second IC die.

18 . The system of claim 16 , wherein:

the first IC die comprises a first of microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry; and

the second IC die comprises a second of microprocessor core circuitry, wireless radio circuitry, FPGA circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry.

19 . The system of claim 16 , further comprising a heat spreader or heat sink on a side of the second IC die opposite the host component.

20 . The system of claim 16 , further comprising second level interconnects (SLI) coupled to a side of the host component opposite the FLI interconnect interfaces, wherein the SLI comprise solder.