Package comprising a chiplet located between an integrated device and a metallization portion

1 . A package comprising:

a first metallization portion;

a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects; and

a first chiplet located between the first integrated device and the first metallization portion,

wherein the first chiplet comprises a trench capacitor device, the first chiplet comprising:

a chiplet substrate;

a plurality of trench capacitors; and

at least one through chiplet substrate interconnect,

wherein the first chiplet comprises a front side and a back side,

wherein the front side of the first chiplet includes the plurality of trench capacitors,

wherein the back side of the first chiplet includes the chiplet substrate, and

wherein the front side of the first chiplet faces in a direction towards the first integrated device,

wherein the first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects, wherein the first plurality of inter pillar interconnects touch the first integrated device.

2 . The package of claim 1 , further comprising an encapsulation layer coupled to the first metallization portion and the first integrated device.

3 . The package of claim 2 , wherein the encapsulation layer comprises:

a first encapsulation layer coupled to the first integrated device; and

a second encapsulation layer coupled to the first metallization portion.

4 . The package of claim 3 , further comprising a dielectric layer located between the first encapsulation layer and the second encapsulation layer, wherein the dielectric layer is coupled to the first encapsulation layer and the second encapsulation layer.

5 . The package of claim 1 , further comprising:

a second integrated device coupled to the first metallization portion through a second plurality of pillar interconnects; and

a second chiplet located between the second integrated device and the first metallization portion, wherein the second chiplet is coupled to the second integrated device through a second plurality of inter pillar interconnects.

6 . The package of claim 5 , further comprising a bridge coupled to the first metallization portion, wherein the bridge is configured to provide at least one electrical path between the first integrated device and the second integrated device.

7 . The package of claim 5 ,

wherein the first chiplet is laterally surrounded by the first plurality of pillar interconnects; and

wherein the second chiplet is laterally surrounded by the second plurality of pillar interconnects.

8 . The package of claim 5 ,

wherein the first integrated device includes a first plurality of die interconnects comprising a first minimum spacing, and

wherein the second integrated device includes a second plurality of die interconnects comprising a second minimum spacing that is different from the first minimum spacing.

9 . The package of claim 8 , wherein the first chiplet includes a plurality of interconnects comprising a third minimum spacing.

10 . The package of claim 1 ,

wherein the first integrated device includes a plurality of die interconnects comprising a first minimum spacing, and

wherein the first chiplet includes a plurality of interconnects comprising a second minimum spacing.

11 . The package of claim 10 , wherein the first minimum spacing is less than the second minimum spacing.

12 . A package comprising:

a first metallization portion;

a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects; and

a first chiplet located between the first integrated device and the first metallization portion,

wherein the first chiplet comprises a trench capacitor device,

wherein the first chiplet comprises a front side and a back side,

wherein the front side of the first chiplet faces in a direction towards the first integrated device,

wherein the first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects, wherein the first plurality of inter pillar interconnects touch the first integrated device,

wherein the first integrated device includes a first plurality of transistors comprising a first minimum spacing, and

wherein the first chiplet includes a second plurality of transistors comprising a second minimum spacing that is different from the first minimum spacing.

13 . A device comprising:

a package comprising:

a first metallization portion;

a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, wherein the first integrated device includes a plurality of die interconnects comprising a first minimum spacing; and

a first chiplet located between the first integrated device and the first metallization portion,

wherein the first chiplet includes a plurality of interconnects comprising a second minimum spacing,

wherein the first minimum spacing is less than the second minimum spacing, and

wherein the first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects.

14 . The device of claim 13 , wherein the first chiplet includes a trench capacitor device.

15 . The device of claim 14 , wherein the first chiplet includes:

a chiplet substrate;

a plurality of trench capacitors; and

at least one through chiplet substrate interconnect,

wherein a front side of the first chiplet includes the plurality of trench capacitors, and

wherein a back side of the first chiplet includes the chiplet substrate.

16 . The device of claim 13 , wherein the first chiplet includes a memory, a power management integrated circuit or a voltage regulator.

17 . The device of claim 13 , wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.

18 . A package comprising:

a first metallization portion;

a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects;

a first chiplet located between the first integrated device and the first metallization portion,

wherein the first chiplet comprises a front side and a back side,

wherein the front side of the first chiplet faces in a direction towards the first integrated device,

wherein the first chiplet includes a memory, a power management integrated circuit or a voltage regulator, and

wherein the first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects, wherein the first plurality of inter pillar interconnects touch the first integrated device;

a second integrated device coupled to the first metallization portion through a second plurality of pillar interconnects; and

a second chiplet located between the second integrated device and the first metallization portion, wherein the second chiplet is coupled to the second integrated device through a second plurality of inter pillar interconnects.

19 . The package of claim 18 , further comprising an encapsulation layer coupled to the first metallization portion and the first integrated device.

20 . The package of claim 19 , wherein the encapsulation layer comprises:

a first encapsulation layer coupled to the first integrated device; and

a second encapsulation layer coupled to the first metallization portion.

21 . The package of claim 20 , further comprising a dielectric layer located between the first encapsulation layer and the second encapsulation layer, wherein the dielectric layer is coupled to the first encapsulation layer and the second encapsulation layer.

22 . The package of claim 20 ,

wherein the first encapsulation layer includes a first concentration of filler, and

wherein the second encapsulation layer includes a second concentration of filler that is different from the first concentration of filler.

23 . The package of claim 22 , wherein the first concentration of filler is higher than the second concentration of filler.

24 . The package of claim 18 , further comprising a bridge coupled to the first metallization portion, wherein the bridge is configured to provide at least one electrical path between the first integrated device and the second integrated device.

25 . The package of claim 18 ,

wherein the first integrated device includes a first plurality of die interconnects comprising a first minimum spacing, and

wherein the second integrated device includes a second plurality of die interconnects comprising a second minimum spacing that is different from the first minimum spacing.

26 . The package of claim 3 ,

wherein the first encapsulation layer includes a first concentration of filler, and

wherein the second encapsulation layer includes a second concentration of filler that is different from the first concentration of filler.

27 . The package of claim 3 ,

wherein the first chiplet is coupled to the first integrated device through the first plurality of inter pillar interconnects and a plurality of solder interconnects, and

wherein the plurality of solder interconnects touch the first plurality of inter pillar interconnects and the first chiplet.

28 . The device of claim 13 ,

wherein the package further comprises an encapsulation layer coupled to the first metallization portion and the first integrated device,

wherein the encapsulation layer comprises:

a first encapsulation layer coupled to the first integrated device; and

a second encapsulation layer coupled to the first metallization portion,

wherein the first encapsulation layer includes a first concentration of filler, and

wherein the second encapsulation layer includes a second concentration of filler that is different from the first concentration of filler.