IP Library Granted Patent US 12685225
Granted Patent B2
US 12685225 · App. 18/325,769 · Granted Jul 14, 2026

Semiconductor device and manufacturing method of the same

Inventors: Takeori Maeda (Mie Mie, JP); Soichi Homma (Yokkaichi Mie, JP)
Assignee: Kioxia Corporation
H10W90/00H10W70/611H10W70/65H10W70/6875H10W70/692H10W95/00H10W72/072
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Quick Facts
Patent No.
US 12685225
App. No.
18/325,769
Granted
Jul 14, 2026
Kind
B2
Abstract

According to one or more embodiments, a semiconductor device includes a support having a recess. A plurality of semiconductor chips are stacked on each other in the recess. A plurality of columnar electrodes in the recess extend from the semiconductor chips toward an opening of the support. A wiring layer is disposed over the opening. The recess is filled with an insulating material to cover the semiconductor chips and the columnar electrodes.

Claims (17)

1 . A method of manufacturing a semiconductor device, the method comprising:

stacking a plurality of semiconductor chips in a recess formed in a support, the recess extending into the support from a first surface;

forming a plurality of columnar electrodes on the semiconductor chips extending upward toward an opening of the recess;

filling an insulating material into the recess to cover the semiconductor chips and the columnar electrodes with the insulating material;

polishing the insulating material until the first surface of the support and an upper end of each of the columnar electrodes are exposed; and

forming a wiring layer on the insulating material and the upper end of each of the columnar electrodes, wherein

the upper end of each of the columnar electrodes extends higher than the first surface of the support, and

the polishing of the insulating material exposes the upper end of each of the columnar electrodes before the first surface.

2 . The method according to claim 1 , wherein the support has a hardness different from a hardness of the insulating material.

3 . The method according to claim 1 , further comprising:

electrically connecting the wiring layer to the columnar electrodes.

4 . The method according to claim 1 , wherein the support comprises a conductive material.

5 . The method according to claim 1 , wherein the support comprises a resin.

6 . The method according to claim 1 , wherein the support comprises a ceramic.

7 . The method according to claim 1 , wherein a lowermost semiconductor chip in the plurality of semiconductor chips in the recess is adhered to a bottom surface of the recess by an adhesive layer.

8 . The method according to claim 1 , wherein semiconductor chips in plurality of semiconductor chips are in tiers offset in a planar direction from one another.

9 . The method according to claim 8 , wherein a lower end of each columnar electrode contacts a tier end portion of the semiconductor chips in the plurality of semiconductor chips.