Semiconductor packages

1 . A semiconductor package comprising:

a substrate including a first region defined as a recess in the substrate and a second region other than the first region;

a three-dimensional (3D) integrated circuit structure disposed on the first region to be non-overlapping vertically with the second region, the 3D integrated circuit structure including a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die;

a plurality of connecting members electrically connecting the first semiconductor chip die to the substrate, wherein a first side of each connecting member of the plurality of connecting members directly contacts the first semiconductor chip die and a second side that is opposite to the first side directly contacts the first region; and

a memory structure disposed on the second region to be non-overlapping vertically with the first region and positioned side by side with the 3D integrated circuit structure.

2 . The semiconductor package of claim 1 , wherein:

a difference between a vertical thickness of the second region and a vertical thickness of the first region is in a range of about 180 μm to about 220 μm.

3 . The semiconductor package of claim 1 , wherein:

a vertical thickness of the first region is in a range of about 115 μm to about 135 μm.

4 . The semiconductor package of claim 1 , wherein:

a vertical thickness of the second region is in a range of about 315 μm to about 335 μm.

5 . The semiconductor package of claim 1 , wherein

a level of an uppermost surface of the second region is between levels of a lowermost surface of the first semiconductor chip die and an uppermost surface of the first semiconductor chip die.

6 . The semiconductor package of claim 1 , wherein:

the second semiconductor chip die includes a communication chip or a sensor.

7 . The semiconductor package of claim 1 , wherein:

the first semiconductor chip die includes a central processing unit (CPU) or graphics processing unit (GPU).

8 . The semiconductor package of claim 1 , wherein:

the first semiconductor chip die includes a plurality of through silicon vias.

9 . The semiconductor package of claim 1 , wherein:

the 3D integrated circuit structure includes a system on chip (SOC).

10 . The semiconductor package of claim 1 , wherein:

the memory structure includes a high-bandwidth memory (HBM).

11 . A semiconductor package comprising:

a substrate including a first region defined as a recess in the substrate and a second region other than the first region;

a redistribution structure disposed on the first region to be non-overlapping vertically with the second region;

a three-dimensional (3D) integrated circuit structure disposed on the redistribution structure to be non-overlapping vertically with the second region, the 3D integrated circuit structure including a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die; and

a memory structure disposed on the second region to be non-overlapping vertically with the first region and positioned side by side with the 3D integrated circuit structure.

12 . The semiconductor package of claim 11 , further comprising:

a molding material on the redistribution structure, the molding material molding the 3D integrated circuit structure.

13 . The semiconductor package of claim 11 , further comprising:

a plurality of connecting members disposed between the redistribution structure and the first region of the substrate, and

at least one capacitor structure on a bottom surface of the redistribution structure.

14 . The semiconductor package of claim 13 , further comprising:

an insulating member surrounding the plurality of connecting members and the at least one capacitor structure between the first region of the substrate and the redistribution structure.

15 . The semiconductor package of claim 14 , wherein:

the insulating member includes a molded under-fill (MUF).

16 . A semiconductor package comprising:

a substrate including a first region defined as a recess in the substrate and a second region other than the first region;

a three-dimensional (3D) integrated circuit structure disposed on the first region to be non-overlapping vertically with the second region, the 3D integrated circuit structure including:

a first semiconductor chip die;

a second semiconductor chip die disposed on the first semiconductor chip die;

a plurality of first connecting members disposed between the first semiconductor chip die and the second semiconductor chip die, the plurality of first connecting members electrically connecting the first semiconductor chip die to the second semiconductor chip die;

an insulating member surrounding the plurality of first connecting members between the first semiconductor chip die and the second semiconductor chip die;

a plurality of second connecting members, wherein a first side of each second connecting member of the plurality of second connecting members directly contacts the first semiconductor chip die and a second side opposite to the first side directly contacts the first region;

a memory structure disposed on the second region to be non-overlapping vertically with the first region and positioned side by side with the 3D integrated circuit structure; and

a molding material molding the 3D integrated circuit structure and the memory structure.

17 . The semiconductor package of claim 16 , wherein:

each first connecting member of the plurality of first connecting members include a micro bump.

18 . The semiconductor package of claim 16 , wherein:

the plurality of second connecting members includes a micro bump.

19 . The semiconductor package of claim 16 , wherein:

the insulating member includes a non-conductive film (NCF).

20 . The semiconductor package of claim 16 , wherein:

the molding material includes an epoxy molding compound (EMC).