Fine pitch chip interconnect structure for bump bridge and high temperature storage improvement and methods for forming the same

1 . An interconnect structure, comprising:

a lower pad comprising:

a first conductive layer having a first diameter; and

a second conductive layer on the first conductive layer and including a second conductive layer lower portion and a second conductive layer upper portion on the second conductive layer lower portion having a second diameter less than the first diameter, wherein an outermost sidewall of the second conductive layer upper portion contacts an upper surface of the first conductive layer and is separated from an outermost sidewall of the first conductive layer;

an upper bump on the lower pad, comprising a first portion, second portion and third portion, wherein the second portion is between the first portion and the third portion, wherein the second portion comprises a material different than a material of the first portion and a material of the third portion, wherein the second portion has a third diameter less than the first diameter and a sidewall of the third portion of the upper bump is over the second conductive layer lower portion; and

a solder joint between the upper bump and the lower pad and including a tapered sidewall having a lower end located at the outermost sidewall of the second conductive layer upper portion and an upper end located at a sidewall of the third portion of the upper bump.

2 . The interconnect structure of claim 1 , wherein a ratio of the first diameter to the third diameter is greater than 1 and less than 3.3.

3 . The interconnect structure of claim 1 , wherein the solder joint connects the upper bump to the lower pad, and comprises tin and at least one of silver, indium, antimony, bismuth or zinc.

4 . The interconnect structure of claim 1 , wherein:

the first conductive layer comprises a nickel layer with a thickness greater than about 3 μm;

the second conductive layer comprises a copper layer with a thickness in a range from 1 μm to 5 μm; and

the solder joint contacting the exposed upper surface of the first conductive layer forms a Cu—Ni—Sn intermetallic compound.

5 . The interconnect structure of claim 1 , wherein a material of the first conductive layer is the same as the material of the second portion of the upper bump, and the second portion of the upper bump has a thickness less than a thickness of the first portion of the upper bump and less than a thickness of the first portion of the upper bump.

6 . The interconnect structure of claim 1 , wherein the third diameter of the second portion of the upper bump is greater than a diameter of the third portion of the upper bump and less than the second diameter of the second conductive layer upper portion.

7 . The interconnect structure of claim 1 , wherein the first conductive layer comprises:

a first conductive layer lower portion; and

a first conductive layer upper portion on the first conductive layer lower portion,

wherein the first diameter of the first conductive layer comprises an outer diameter of the first conductive layer upper portion.

8 . The interconnect structure of claim 7 , wherein the second conductive layer upper portion comprises a second recess that is substantially aligned with the first recess of the first conductive layer upper portion, the second recess is bounded by an inner sidewall of the second conductive layer upper portion located over the first conductive layer lower portion, and a diameter of the second recess is less than the third diameter of the second portion of the upper bump.

9 . The interconnect structure of claim 8 , wherein the solder joint comprises:

a main body extending from the upper bump to an upper surface of the second conductive layer upper portion; and

an extension portion that extends from the main body into the second recess of the second conductive layer upper portion.

10 . The interconnect structure of claim 8 , wherein the second recess in the second conductive layer upper portion includes a diameter that is in a range from 40% to 70% of the second diameter, and a depth that is greater than 0.2 μm.

11 . The interconnect structure of claim 7 , wherein the first conductive layer upper portion comprises a first substantially planar upper surface and the outer diameter of the first conductive layer upper portion comprises an outer diameter of the first substantially planar upper surface.

12 . The interconnect structure of claim 11 , wherein the second conductive layer is on the first substantially planar upper surface and comprises a second substantially planar upper surface and the outer diameter of the second conductive layer upper portion comprises an outer diameter of the second substantially planar upper surface.

13 . The interconnect structure of claim 12 , wherein the solder joint comprises a substantially planar bottom surface contacting the second substantially planar upper surface of the second conductive layer and having an outer diameter substantially the same as the outer diameter of the second substantially planar upper surface.

14 . The interconnect structure of claim 1 , wherein the tapered sidewall extends linearly from the outermost sidewall of the second conductive layer upper portion to the sidewall of the third portion of the upper bump.

15 . A method of forming an interconnect structure, the method comprising:

forming a lower pad comprising:

a metallization layer;

a first conductive layer on the metallization layer and having a first diameter; and

a second conductive layer on the first conductive layer and including a second conductive layer lower portion and a second conductive layer upper portion on the second conductive layer lower portion having a second diameter less than the first diameter, wherein an outermost sidewall of the second conductive layer upper portion is located over the metallization layer, contacts an upper surface of the first conductive layer and is separated from an outermost sidewall of the first conductive layer;

forming an upper bump having a third diameter less than the first diameter;

forming a solder material on the upper bump;

positioning the upper bump over the lower pad such that a sidewall of the upper bump is over the lower portion of the second conductive layer; and

reflowing the solder material to form a solder joint between the upper bump and the lower pad such that the solder joint includes a tapered sidewall having a lower end located at the outermost sidewall of the second conductive layer upper portion and an upper end located at a sidewall of the upper bump.

16 . The method of claim 15 , wherein the first conductive layer contacts an upper surface of the metallization layer and the second conductive layer contacts an upper surface of the first conductive layer.

17 . The method of claim 15 , wherein the forming of the upper bump comprises:

forming a first pillar including a first pillar material;

forming a second pillar on the first pillar, the second pillar including a second pillar material different than the first pillar material; and

forming a third pillar on the second pillar, the third pillar including the first pillar material, and

wherein the forming of the solder material comprises forming the solder material on the third pillar.

18 . The method of claim 15 , wherein the forming of the lower pad comprises forming a second recess in the second conductive layer, and the reflowing of the solder material comprises reflowing the solder material into the second recess.

19 . The method of claim 15 , wherein the forming of the lower pad comprises forming a second substantially planar upper surface on the second conductive layer, and the reflowing of the solder material comprises reflowing the solder material onto the second substantially planar upper surface.

20 . A package assembly, comprising:

a package substrate;

an interposer module on the package substrate and connected to the package substrate by a first interconnect structure, the interposer module comprising:

an interlayer dielectric; and

a plurality of semiconductor dies on the interlayer dielectric and connected to the interlayer dielectric by a second interconnect structure,

wherein at least one of the first interconnect structure or the second interconnect structure comprises:

a lower pad comprising:

a metallization layer;

a first conductive layer on the metallization layer and having a first diameter and including a first recess; and

a second conductive layer on the first conductive layer and in the first recess, wherein the second conductive layer includes a second conductive layer lower portion and a second conductive layer upper portion on the second conductive layer lower portion having a second diameter less than the first diameter, and wherein the second conductive layer upper portion includes a second recess and an outermost sidewall of the second conductive layer upper portion is located over the metallization layer, contacts an upper surface of the first conductive layer and is separated from an outermost sidewall of the first conductive layer;

an upper bump on the lower pad and having a third diameter less than the first diameter,

wherein a sidewall of the upper bump is over the second conductive layer lower portion; and

a solder joint between the upper bump and the lower pad and in the second recess of the second conductive layer, wherein the solder joint includes a tapered sidewall having a lower end located at the outermost sidewall of the second conductive layer upper portion and an upper end located at a sidewall of the upper bump.