Systems and methods for mitigating stimulation current spikes and glitches in neurostimulation systems

1 . An implantable pulse generator (IPG) for use in a neurostimulation system, the IPG comprising:

a case;

pulse generating circuitry configured to generate stimulation pulses to be applied to a patient at an output of the IPG;

voltage multiplier circuitry configured to step an output voltage to an anode of the pulse generating circuitry; and

glitch mitigating circuitry configured to mitigate current glitches generated when the output voltage is stepped during generation of a stimulation pulse to be applied to the patient, wherein the glitch mitigating circuitry comprises:

a first step switch connected to the case;

a second step switch connected to a cathode of the pulse generating circuitry;

a first glitch mitigation capacitor connected to the first step switch, wherein the first glitch mitigation capacitor is connected to the case and the anode when the first step switch is in a closed position; and

a second glitch mitigation capacitor connected to the second step switch, wherein the second glitch mitigation capacitor is connected to the cathode and the anode when the second step switch is in a closed position.

2 . The IPG of claim 1 , wherein the IPG is configured to deliver stimulation pulses to target tissue for spinal cord stimulation (SCS).

3 . The IPG of claim 1 , wherein the IPG is configured to deliver stimulation pulses to target tissue for deep brain stimulation (DBS).

4 . The IPG of claim 1 , wherein the glitch mitigation circuitry further comprises first and second no-step switches, wherein the first and second step switches and the first and second no-step switches cooperate to selectively connect and disconnect the first and second glitch mitigation capacitors.

5 . The IPG of claim 1 , wherein the glitch mitigation circuitry further comprises a first step switch in parallel with the first glitch mitigation capacitor, and a second step switch in parallel with the second glitch mitigation capacitor.

6 . The IPG of claim 1 , wherein the first and second glitch mitigation capacitors have a capacitance greater than 10 nano Farads.

7 . The IPG of claim 1 , wherein the first and second glitch mitigation capacitors have a capacitance of approximately 20 pico Farads.

8 . A neurostimulation system comprising:

an implantable stimulation lead comprising a plurality of contacts; and

an implantable pulse generator (IPG) communicatively coupled to the implantable stimulation lead, the IPG comprising:

a case;

pulse generating circuitry configured to generate stimulation pulses to be applied to a patient through the implantable stimulation lead;

voltage multiplier circuitry configured to step an output voltage to an anode of the pulse generating circuitry; and

glitch mitigating circuitry configured to mitigate current glitches generated when the output voltage is stepped during generation of a stimulation pulse to be applied to the patient, wherein the glitch mitigation circuitry comprises:

a first step switch connected to the case:

a second step switch connected to a cathode of the pulse generating circuitry;

a first glitch mitigation capacitor connected to the first step switch, wherein the first glitch mitigation capacitor is connected to the case and the anode when the first step switch is in a closed position; and

a second glitch mitigation capacitor connected to the second step switch, wherein the second glitch mitigation capacitor is connected to the cathode and the anode when the second step switch is in a closed position.

9 . The neurostimulation system of claim 8 , wherein the neurostimulation system is a spinal cord stimulation (SCS) system.

10 . The neurostimulation system of claim 8 , wherein the neurostimulation system is a deep brain stimulation (DBS) system.

11 . The neurostimulation system of claim 8 , wherein the glitch mitigation circuitry further comprises first and second no-step switches, wherein the first and second step switches and the first and second no-step switches cooperate to selectively connect and disconnect the first and second glitch mitigation capacitors.

12 . The neurostimulation system of claim 8 , wherein the glitch mitigation circuitry further comprises a first step switch in parallel with the first glitch mitigation capacitor, and a second step switch in parallel with the second glitch mitigation capacitor.

13 . The neurostimulation system of claim 8 , wherein the first and second glitch mitigation capacitors have a capacitance greater than 10 nano Farads.

14 . The neurostimulation system of claim 8 , wherein the first and second glitch mitigation capacitors have a capacitance of approximately 20 pico Farads.

15 . A method of applying neurostimulation, the method comprising:

generating, using an implantable pulse generator (IPG), a pulse to be delivered to a patient, wherein the IPG includes a case;

stepping an output voltage to an anode of the IPG while the pulse is being delivered to the patient; and

mitigating, using glitch mitigation circuitry, a current glitch generated by the stepped output voltage during generation of a pulse to be delivered to the patient, wherein the glitch mitigation circuitry comprises:

a first step switch connected to the case;

a second step switch connected to a cathode of the pulse generating circuitry;

a first glitch mitigation capacitor connected to the first step switch, wherein the first glitch mitigation capacitor is connected to the case and the anode when the first step switch is in a closed position; and

a second glitch mitigation capacitor connected to the second step switch, wherein the second glitch mitigation capacitor is connected to the cathode and the anode when the second step switch is in a closed position.

16 . The method of claim 15 , wherein the IPG is configured to deliver stimulation pulses to target tissue for spinal cord stimulation (SCS).

17 . The method of claim 15 , wherein the IPG is configured to deliver stimulation pulses to target tissue for deep brain stimulation (DBS).