IP Library Granted Patent US 12686923
Granted Patent B2
US 12686923 · App. 18/482,560 · Granted Jul 21, 2026

Arc reduction and RF control for electrostatic chucks in semiconductor processing

Inventors: Allison Yau (Mountain View, CA); Manoj Kumar Jana (San Jose, CA); Wen-Shan Lin (San Jose, CA); Zhiling Dun (Campbell, CA); Xinhai Han (Palo Alto, CA); Deenesh Padhi (Saratoga, CA); Jian Li (Fremont, CA); Yuanchang Chen (Santa Clara, CA); Wenhao Zhang (San Jose, CA); Edward P. Hammond (Hillsborough, CA); Alexander V. Garachtchenko (Brentwood, CA); Ganesh Balasubramanian (Fremont, CA); Juan Carlos Rocha-Alvarez (San Carlos, CA); Sathya Ganta (Sunnyvale, CA)
Assignee: Applied Materials, Inc.
C23C16/4586C23C16/34C23C16/401H01J37/32174H01J37/32697H01J37/32715H01J2237/3321
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12686923
App. No.
18/482,560
Granted
Jul 21, 2026
Kind
B2
Abstract

A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.

Claims (29)

1 . A semiconductor processing chamber comprising:

a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate;

one or more internal meshes embedded in the pedestal, wherein the one or more internal meshes are configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process;

an RF source configured to deliver the RF power to the one or more internal meshes;

one or more variable capacitors coupled between the RF source and the one or more internal meshes, wherein adjusting a capacitance of the one or more variable capacitors adjusts an amount of the RF power that is provided to the one or more internal meshes; and

a controller configured to adjust the capacitance of the one or more variable capacitors to adjust the amount of the RF power that is provided to the one or more internal meshes and cause a horizontal component of an electric field that directs ions from the plasma to a periphery of the substrate when forming the film.

2 . The semiconductor processing chamber of claim 1 , wherein the one or more internal meshes comprises a plurality of internal meshes.

3 . The semiconductor processing chamber of claim 1 , wherein the one or more internal meshes comprises a single internal mesh.

4 . The semiconductor processing chamber of claim 1 , wherein the one or more internal meshes comprises two hemispherical meshes.

5 . The semiconductor processing chamber of claim 1 , further comprising:

an external mesh having a ring-shape that encircles the one or more internal meshes; and

a variable capacitor coupled between the RF source and the external mesh, wherein adjusting the capacitance of the variable capacitor adjusts an amount of the RF power that is provided to the external mesh.

6 . The semiconductor processing chamber of claim 5 , the controller is programmed to adjust the variable capacitor and the one or more variable capacitors during the PECVD process to adjust the amount of RF power delivered to the one or more internal meshes and the amount of RF power delivered to the external mesh.

7 . The semiconductor processing chamber of claim 1 , further comprising a substrate on the pedestal, wherein a diameter of the one or more internal meshes is less than a diameter of the substrate such that the substrate entirely covers the one or more internal meshes when supported by the pedestal.

8 . The semiconductor processing chamber of claim 1 , wherein an outer diameter of the one or more internal meshes is less that a diameter of the substrate.

9 . The semiconductor processing chamber of claim 1 , further comprising:

a substrate on the pedestal in the semiconductor processing chamber, wherein the substrate comprises a film formed on a surface of the substrate in the semiconductor processing chamber.

10 . The semiconductor processing chamber of claim 9 , wherein the film comprises one or more alternating layers of oxide and nitride.

11 . The semiconductor processing chamber of claim 9 , wherein the film comprises a layer of oxide comprising a thickness of more than 25 μm.

12 . A semiconductor processing chamber comprising:

a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate;

one or more internal meshes embedded in the pedestal, wherein the one or more internal meshes are configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process, and an outer diameter of the one or more internal meshes is less that a diameter of the substrate;

an RF source configured to deliver the RF power to the one more internal meshes; and

a controller configured to adjust an amount of the RF power that is provided to the one or more internal meshes and cause a horizontal component of an electric field that directs ions from the plasma to a periphery of the substrate when forming the film.

13 . The semiconductor processing chamber of claim 12 , wherein the diameter of the substrate is between 0 mm and 5 mm greater than the outer diameter of the one or more internal meshes.

14 . The semiconductor processing chamber of claim 12 , wherein the outer diameter of the one or more meshes is between 95% and 99% of the diameter of the substrate.

15 . The semiconductor processing chamber of claim 12 , further comprising a substrate on the pedestal, and an external mesh that is ring-shaped and surrounds the one or more internal meshes, and an inner diameter of the external mesh is greater than the diameter of the substrate.

16 . The semiconductor processing chamber of claim 12 , further comprising a substrate on the pedestal, wherein a difference between the outer diameter of the one or more internal meshes and the diameter of the substrate is sufficient to eliminate arcing from the one or more internal meshes during the PECVD process.

17 . The semiconductor processing chamber of claim 12 , further comprising a substrate on the pedestal, wherein the pedestal does not include an external mesh that surrounds the one or more internal meshes such that any meshes that deliver the RF power to the plasma are covered by the substrate on the pedestal.