SiC substrate, SiC substrate production method, SiC semiconductor device, and SiC semiconductor device production method
View Patent ↗The present invention addresses the issue of providing: an SiC substrate having a dislocation conversion layer that can reduce resistance; and a novel technology pertaining to SiC semiconductors. This SiC substrate and SiC semiconductor device comprise a dislocation conversion layer 12 having a doping concentration of at least 1×10 15 cm −3 . As a result of comprising a dislocation conversion layer 12 having this kind of doping concentration: expansion of basal plane dislocations and the occurrence of high-resistance stacking faults can be suppressed; and resistance when SiC semiconductor devices are produced can be reduced.
1 . A SiC substrate comprising a base substrate and a dislocation conversion layer having a doping concentration of 1×10 15 cm −3 or more,
wherein the dislocation conversion layer is a single layer formed directly above the base substrate and has a conversion rate from the basal plane dislocation to the threading edge dislocation of more than 95%, and
wherein, in the base substrate, a subsurface damaged layer is removed and a macro-step bunching is decomposed such that the base substrate has a main surface having steps of one unit cell height.
2 . The SiC substrate according to claim 1 , comprising a dislocation conversion layer having a doping concentration of 1×10 17 cm −3 or more.
3 . The SiC substrate according to claim 1 , wherein the dislocation conversion layer has a thickness of 1 μm or more.
4 . The SiC substrate according to claim 1 , wherein the dislocation conversion layer has a conversion rate from the basal plane dislocation to the threading edge dislocation of 100%.
5 . The SiC substrate according to claim 1 , further comprising an epitaxial growth layer formed directly above the dislocation conversion layer,
wherein the doping concentration of the dislocation conversion layer is higher than the doping concentration of the epitaxial growth layer.
6 . A SiC semiconductor device comprising a base substrate and a dislocation conversion layer having a doping concentration of 1×10 15 cm −3 or more,
wherein the dislocation conversion layer is a single layer formed directly above the base substrate and has a conversion rate from the basal plane dislocation to the threading edge dislocation of more than 95%, and
wherein, in the base substrate, a subsurface damaged layer is removed and a macro-step bunching is decomposed such that the base substrate has a main surface having steps of one unit cell height.
7 . The SiC semiconductor device according to claim 6 , comprising a dislocation conversion layer having a doping concentration of 1×10 17 cm −3 or more.
8 . The SiC semiconductor device according to claim 6 , wherein the dislocation conversion layer has a thickness of 1 μm or more.
9 . The SiC semiconductor device according to claim 6 , wherein the dislocation conversion layer has a conversion rate from the basal plane dislocation to the threading edge dislocation of 100%.
10 . The SiC semiconductor device according to claim 6 , further comprising an epitaxial growth layer formed directly above the dislocation conversion layer,
wherein the doping concentration of the dislocation conversion layer is higher than the doping concentration of the epitaxial growth layer.