IP Library › Granted Patent US 12687572
Granted Patent B2
US 12687572 · App. 18/581,263 · Granted Jul 21, 2026

Test method

Inventor: Kenichi Ishii (Matsumoto-city, JP)
Assignee: FUJI ELECTRIC CO., LTD.
G01R31/2608G01R31/2621
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Quick Facts
Patent No.
US 12687572
App. No.
18/581,263
Granted
Jul 21, 2026
Kind
B2
Abstract

A test method of testing a test target transistor device is provided, the test method including: arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire; and causing a gate voltage applied to the test transistor device to be higher than a gate voltage applied to the test target transistor device. A difference between the gate voltage applied to the test transistor device and the gate voltage applied to the test target transistor device may be 5.0 V or less.

Claims (49)

1 . A test method of testing a test target transistor device, comprising:

arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire; and

causing a gate voltage applied to the test transistor device to be higher than a gate voltage applied to the test target transistor device, wherein

the gate voltage of the test transistor device is adjustable for every test target transistor device that is the test target transistor device.

2 . The test method according to claim 1 , wherein

the test transistor device is arranged between the test target transistor device and the high voltage side wire.

3 . The test method according to claim 1 , wherein

a difference between the gate voltage applied to the test transistor device and the gate voltage applied to the test target transistor device is 5.0 V or less.

4 . The test method according to claim 1 , wherein

the gate voltage of the test target transistor device and the gate voltage of the test transistor device are controlled such that a test current defined by a test specification flows into the test target transistor device.

5 . The test method according to claim 4 , wherein

when the gate voltage of the test transistor device is increased more, the gate voltage of the test target transistor device is decreased more.

6 . The test method according to claim 1 , wherein

the gate voltage of the test transistor device and a power supply voltage applied to the high voltage side wire are controlled such that a test current defined by a test specification flows into the test target transistor device.

7 . The test method according to claim 6 , wherein

when the gate voltage of the test transistor device is increased more, the power supply voltage is decreased more.

8 . The test method according to claim 1 , wherein

the gate voltage of the test transistor device and a test time in which a test current flows into the test target transistor device are controlled such that energy defined by a test specification is applied to the test target transistor device.

9 . The test method according to claim 8 , wherein

when the gate voltage of the test transistor device is increased more, the test time is shortened more.

10 . The test method according to claim 1 , wherein

the gate voltage of the test transistor device and temperature of a stage on which the test target transistor device is mounted are controlled such that a test current defined by a test specification flows into the test target transistor device.

11 . The test method according to claim 10 , wherein

when the gate voltage of the test transistor device is increased more, the temperature of the stage is decreased more.

12 . The test method according to claim 1 , wherein

the gate voltage of the test transistor device is controlled based on a size of a pad of the test target transistor device.

13 . The test method according to claim 1 , wherein:

multiple types of probes to be connected to a pad of the test target transistor device are prepared; and

the gate voltage of the test transistor device is controlled based on a type of a probe connected to the pad of the test target transistor device among the multiple types of probes.

14 . The test method according to claim 1 , wherein

on a stage for mounting the test target transistor device, a mounting surface on which the test target transistor device is mounted is gold plated.

15 . The test method according to claim 2 , wherein

the gate voltage of the test target transistor device and the gate voltage of the test transistor device are controlled such that a test current defined by a test specification flows into the test target transistor device.

16 . The test method according to claim 3 , wherein

the gate voltage of the test target transistor device and the gate voltage of the test transistor device are controlled such that a test current defined by a test specification flows into the test target transistor device.

17 . The test method according to claim 2 , wherein

the gate voltage of the test transistor device and a power supply voltage applied to the high voltage side wire are controlled such that a test current defined by a test specification flows into the test target transistor device.

18 . The test method according to claim 3 , wherein

the gate voltage of the test transistor device and a power supply voltage applied to the high voltage side wire are controlled such that a test current defined by a test specification flows into the test target transistor device.

19 . The test method according to claim 2 , wherein

the gate voltage of the test transistor device and a test time in which a test current flows into the test target transistor device are controlled such that energy defined by a test specification is applied to the test target transistor device.

20 . A test method of testing a test target transistor device, comprising:

arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire; and

causing a gate voltage applied to the test transistor device to be higher than a gate voltage applied to the test target transistor device, wherein

the gate voltage of the test transistor device is controlled based on a size of a pad of the test target transistor device.

21 . A test method of testing a test target transistor device, comprising:

arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire; and

causing a gate voltage applied to the test transistor device to control the test transistor device to be in an ON state to be higher than a gate voltage applied to the test target transistor device to control the test target transistor device to be in an ON state, wherein the testing is for a short circuit,

wherein the gate voltage of the test transistor device is adjustable for every test target transistor device that is the test target transistor device.