IP Library Granted Patent US 12687754
Granted Patent B2
US 12687754 · App. 18/735,226 · Granted Jul 21, 2026

Display apparatus

Inventor: Hirotaka Hayashi (Tokyo, JP)
Assignee: MAGNOLIA WHITE CORPORATION
G02F1/136286G02F1/1339
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Quick Facts
Patent No.
US 12687754
App. No.
18/735,226
Granted
Jul 21, 2026
Kind
B2
Abstract

Some of a plurality of image signal lines of a display apparatus according to one embodiment includes: a plurality of bypass wiring portions (bypass wirings) arranged in a frame region so as to have both ends being connected to a plurality of extension wiring portions (extension wirings). The plurality of bypass wiring portions of the plurality of image signal lines include: a plurality of second-layer bypass wirings arranged in a second conductive layer; and a plurality of third-layer bypass wirings arranged in a third conductive layer that is different from a first conductive layer and the second conductive layer. Each of an arrangement pitch between the plurality of second-layer bypass wirings and an arrangement pitch between the plurality of third-layer bypass wirings is smaller than an arrangement pitch between the plurality of image signal lines in a display region.

Claims (24)

1 . An array substrate comprising:

a plurality of pixels arranged in a display region;

a transparent region, that is a region where the plurality of pixels is not arranged, arranged inside the display region;

a frame region formed between the display region and the transparent region so as to surround the transparent region;

a plurality of scan signal lines formed in a first conductive layer, each of the plurality of scan signal lines close to the transparent region including a first bypass wiring;

a plurality of image signal lines formed in a second conductive layer, each of the plurality of image signal lines close to the transparent region including a second bypass wiring; and

a plurality of third-layer bypass wirings formed in a third conductive layer, wherein

each of the first bypass wirings and the second bypass wirings extends along the transparent region in the frame region, and the first bypass wirings and the second bypass wirings are curving along with each other, and

in a plan view, each of the plurality of third-layer bypass wirings extends along the second bypass wiring and is located between two adjacent of second bypass wirings.

2 . The array substrate of claim 1 , wherein the third conductive layer is positioned above the second conductive layer, and the second conductive layer is positioned above the first conductive layer.

3 . The array substrate of claim 1 , wherein the transparent region is a region corresponding to a position where a camera overlaps.

4 . The array substrate of claim 1 , wherein, in the frame region,

each of the plurality of image signal line includes a first end and a second end,

each of the plurality of image signal line is divided between the first end and the second end, and

the second bypass wiring connects between the first end and the second end.

5 . The array substrate of claim 1 , wherein

the second bypass wiring does not overlap the two adjacent first bypass wirings.

6 . The array substrate of claim 1 , wherein

the second bypass wiring overlaps one of the two adjacent first bypass wirings, and

the second bypass wiring does not overlap another of the two adjacent first bypass wirings.

7 . The array substrate of claim 1 , further comprising:

an inorganic insulating film provided between the first conductive layer and the second conductive layer.

8 . The array substrate of claim 7 , further comprising:

an organic insulating film provided between the second conductive layer and the third conductive layer.