IP Library Granted Patent US 12687791
Granted Patent B2
US 12687791 · App. 17/749,037 · Granted Jul 21, 2026

Workpiece support

Inventors: Ming-Yi Shen (Hsinchu, TW); Yao Fong Dai (Hsinchu, TW); Yin-Tun Chou (Hsinchu, TW); Yuan-Hsin Chi (Hsinchu, TW); Sheng-Yuan Lin (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
G03F7/707G03F7/70716
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Quick Facts
Patent No.
US 12687791
App. No.
17/749,037
Granted
Jul 21, 2026
Kind
B2
Abstract

The present disclosure is directed to workpiece support for supporting a workpiece during semiconductor processing. The workpiece support includes one or more support frame bodies including a plurality of spaced apart spacers on a first surface of the support frame bodies. The spacers include a first surface spaced apart from the first surface of the support frame body. The spacing between the first surface of the spacers and the first surface of the support frame body results in the underside of the workpiece contacting the spacers but not contacting the first surface of the support frame body. Portions of the underside of the workpiece that do not contact the first surface of the support frame body are less susceptible to damage or accumulation of unwanted debris.

Claims (33)

1 . A workpiece support, comprising:

a base, the base including a first surface and a second surface opposite the first surface, in operation, the base supporting a semiconductor wafer that includes a lithography frame region in which circuits are to be patterned via lithography, the lithography frame region having a first length dimension and a first width dimension;

a first support frame on the first surface, the first support frame including a first support frame body having a first surface and a second surface opposite the first surface; and

a plurality of spaced apart first spacers that extend outward from the first surface of the first support frame body, the plurality of spaced apart first spacers are first pin supports, each respective first pin support of the plurality of first pin supports including a first workpiece contact surface that is spaced outward from the first surface of the first support frame body;

wherein the first support frame and each respective first pin support of the plurality of spaced apart first pin supports are entirely overlapped by the semiconductor wafer outside the lithography frame region when the semiconductor wafer is on the workpiece support, and are exposed by the lithography frame region such that the support frame and the plurality of first pin supports contacts are separate from the lithography frame region; and

wherein each of the first workpiece contact surfaces of each respective first pin support of the plurality of first pin supports are sized and arranged to contact an underside of the semiconductor wafer outside the lithography frame region and leave the lithography frame region uncovered, and the plurality of first pin supports are configured to, in operation, support the semiconductor wafer in a position with the first workpiece contact surfaces of each respective first pin support of the plurality of first pin supports and space apart an underside surface of the semiconductor wafer from the first support frame body.

2 . The workpiece support of claim 1 , wherein the first support frame body of the first support frame is integral with the base.

3 . The workpiece support of claim 2 , wherein the first support frame body has a second length dimension and two respective first pin supports of the plurality of first pin supports are spaced apart by a first distance and the second length dimension is greater than the first distance.

4 . The workpiece support of claim 3 , wherein the first distance is 50% or more of the second length dimension.

5 . The workpiece support of claim 1 , wherein the first workpiece contact surface of each respective first pin support of the plurality of pin supports is formed of an inert material.

6 . The workpiece support of claim 1 , wherein each respective first pin support of the plurality of first pin supports is polygonal in shape.

7 . The workpiece support of claim 1 , further comprising a second support frame on the first surface of the base.

8 . The workpiece support of claim 7 , wherein the second support frame includes a second support frame body having a third surface and a fourth surface opposite the second surface and a plurality of spaced apart second spacers that extend outward from the third surface of the second support frame body, the plurality of spaced apart second spacers are second pin supports, and each respective second pin support of the plurality of second pin supports includes a second workpiece contact surface that is spaced outward from the third surface of the second support frame body of the second support frame.

9 . The workpiece support of claim 8 , wherein the entire second support frame, is overlapped by the semiconductor wafer when the semiconductor wafer is on the workpiece support and is uncovered by the lithography frame region.

10 . The workpiece support of claim 8 , wherein the first support frame and the second support frame are spaced apart by a second distance which is greater than the first width dimension.

11 . The workpiece support of claim 7 , wherein the first support frame includes two first pin supports and the second support frame includes only one second spacer, and the second spacer is a second pin support.

12 . A workpiece support, comprising:

a base, the base including a first surface and a second surface opposite the first surface, the workpiece being a semiconductor wafer having a lithography frame region on the semiconductor wafer for circuit patterning, the lithography frame region having a first dimension and a second dimension;

two support frames on the first surface of the base, each respective support frame of the two support frames are located entirely outside the lithography frame region, each support frame of the two support frames including a support frame body having a length dimension, a third surface, and a fourth surface opposite the third surface, the two support frames spaced apart by a third dimension that is greater than the length dimension;

a plurality of spaced apart pin supports that extend outward from the first surface of each respective support frame body of the two support frames, each respective pin support of the plurality of pin supports including a workpiece contact surface spaced apart from the first surface of a corresponding support frame body of the two support frames;

wherein each support frame of the two support frames and each respective pin support of the plurality of pin supports are fully overlapped by the semiconductor wafer and is separate from the lithography frame region, such that the lithography frame region remains uncovered;

wherein an underside of the semiconductor wafer contacts the workpiece contact surfaces of the plurality of pin supports outside the lithography frame region to avoid contact with the lithography frame region, and the plurality of pin supports are configured to, in operation, support the semiconductor wafer in a position with the workpiece contact surfaces of each respective pin support of the plurality of pin supports and space apart the underside surface of the semiconductor wafer from the respective support frame body of the two support frames.

13 . The workpiece support of claim 12 , wherein the first dimension is less than the second dimension.

14 . The workpiece support of claim 12 , wherein the two support frames are parallel with each other.

15 . The workpiece support of claim 12 , wherein the respective pin supports of the plurality of pin supports that extend from each respective support frame body of the two support frames are spaced apart by a fourth dimension which is 50% or more of the first dimension.

16 . The workpiece support of claim 12 , wherein the respective pin supports of the plurality of pin supports that extend from each respective support frame body of the two support frames are spaced apart by a fourth dimension which is 50% or more of the length dimension.

17 . A method, comprising:

delivering a workpiece in the form of a semiconductor wafer to a workpiece support, the workpiece support including a base having a first surface, a second surface opposite the first surface, and a pair of support frame bodies on the first surface, each respective support frame body of the pair of support frame bodies including a plurality of spaced apart spacers that extend outward from each respective support frame body of the pair of support frame bodies, the plurality of spaced apart spacers are pin supports, the semiconductor wafer including a lithography frame region having a length dimension and a width dimension defining an area for circuit lithography, each of the pair of support frame bodies are exposed by the lithography frame;

contacting an underside of the semiconductor wafer outside the lithography frame region with the plurality of pin supports on a respective surface of each respective support frame body of the pair of support frame bodies, the plurality of pin supports extend outward from each respective surface of each respective support frame body of the pair of support bodies; and

overlapping the two support frame bodies and the plurality of pin supports with portions of the semiconductor wafer lying outside the lithography frame region, so that the lithography frame region remains uncovered, each respective pin support of the plurality of pin supports including a workpiece contact surface spaced apart from a corresponding respective surface of each respective support frame body of the pair of support frame bodies, the pair of support frame bodies being spaced apart by a width distance that is greater than the width dimension of the lithography frame region, and the plurality of pin supports space apart the underside of the semiconductor wafer from each respective surface of the respective support-bodies frame body of the pair of support bodies.

18 . The method of claim 17 , further comprising processing the semiconductor wafer while the underside of the semiconductor wafer contacts the plurality of spaced apart spacers.

19 . The method of claim 18 , wherein the processing the semiconductor wafer while the underside of the semiconductor wafer contacts the plurality of spaced apart spacers further includes processing the semiconductor wafer on the workpiece support while portions of the underside of the semiconductor wafer are not in contact with portions of the pair of support frame bodies that are overlapped by the semiconductor wafer.

20 . The method of claim 18 , wherein the processing the workpiece while the underside of the workpiece contacts the plurality of spaced apart spacers further includes processing the workpiece on the workpiece support while portions of the underside of the workpiece are spaced apart from the first surface of the pair of support frame bodies.