Regulator circuit for accepting range of input voltages while achieving lower power consumption

1 . A regulator circuit comprising:

a power transistor that controls a supply of current to an external output terminal connected to a load;

a monitor transistor that is provided between the external output terminal and a reference voltage terminal to which a reference voltage is supplied, and through which a first current flows in accordance with a voltage of the external output terminal;

a first constant current source that is provided in series with the monitor transistor and generates a first voltage in accordance with a difference between the first current and a first constant current; and

a cascode circuit that generates a second voltage by amplifying the first voltage and supplies it to a gate of the power transistor,

wherein the power transistor is a P-channel MOS transistor,

wherein the monitor transistor is a P-channel MOS transistor,

wherein the cascode circuit includes a first transistor which is a P-channel MOS transistor to which the first voltage is supplied at a gate of the first transistor and the reference voltage is supplied at a drain of the first transistor, a second transistor which is an N-channel MOS transistor provided in series with the first transistor and to which a predetermined voltage is supplied at a gate of the second transistor, and a second constant current source which is provided in series with the first and second transistors and outputs a second constant current, and

wherein the cascode circuit generates the second voltage in accordance with the second constant current and resistance values of the first and second transistors.

2 . The regulator circuit according to claim 1 ,

wherein the first transistor has a gate oxide film thickness thinner than that of a gate oxide film of the power transistor.

3 . The regulator circuit according to claim 2 ,

wherein the monitor transistor has a gate oxide film thickness thinner than that of the gate oxide film of the power transistor.

4 . The regulator circuit according to claim 1 ,

wherein the monitor transistor has a gate oxide film thickness thinner than that of a gate oxide film of the power transistor.

5 . The regulator circuit according to claim 1 ,

wherein the second transistor is a depletion-type N-channel MOS transistor.

6 . The regulator circuit according to claim 1 , further comprising a first capacitive element provided between the source and drain of the monitor transistor.

7 . The regulator circuit according to claim 6 , further comprising a second capacitive element provided between the gate and source of the first transistor.

8 . The regulator circuit according to claim 1 , further comprising a capacitive element provided between the gate and source of the first transistor.

9 . The regulator circuit according to claim 1 ,

wherein the second constant current source is a resistive element.

10 . The regulator circuit according to claim 1 , further comprising an amplifier that generates a control voltage in accordance with a feedback voltage corresponding to the voltage of the external output terminal and the reference voltage, and supplies it to the gate of the monitor transistor.

11 . The regulator circuit according to claim 10 ,

wherein the amplifier is driven by the voltage of the external output terminal and is composed of a plurality of transistors having a gate oxide film thickness thinner than that of a gate oxide film of the power transistor.

12 . The regulator circuit according to claim 11 , further comprising a resistive element provided between the drain of the power transistor and the external output terminal.