Voltage reference circuit using field-effect transistors

1 . An integrated circuit, comprising:

a first temperature-sensitive device, configured to generate a reference voltage at an output terminal of the integrated circuit;

a second temperature-sensitive device, coupled to the output terminal of the integrated circuit through a resistor, and configured to operate in conjunction with the first temperature-sensitive device to generate a first bias current which flows from the output terminal of the integrated circuit to a ground node through the resistor and the first temperature-sensitive device,

wherein the first bias current monotonically increases as an absolute temperature of the integrated circuit increases; and

a trimming circuit comprising a plurality of trimming stacked gate devices, and configured to adjust a number of the trimming stacked gate devices that are coupled in parallel with the second temperature-sensitive device.

2 . The integrated circuit of claim 1 , wherein the resistor is coupled between the output terminal of the integrated circuit and a first node, and the integrated circuit further comprises a current source, coupled to the second temperature-sensitive device, and configured to generate a second bias current, which is substantially equal to the first bias current, flowing through the second temperature-sensitive device.

3 . The integrated circuit of claim 2 , wherein the first temperature-sensitive device comprises a first stacked gate device having a gate terminal connected to the output terminal of the integrated circuit, a first terminal connected to the first node, and a second terminal connected to the ground node; and

the first stacked gate device comprises one or more first finger structures arranged in parallel, with each first finger structure comprising a first number of field-effect transistors connected in series.

4 . The integrated circuit of claim 3 , wherein the second temperature-sensitive device comprises a second stacked gate device having a gate terminal connected to the first node of the integrated circuit, a first terminal connected to a second node, and a second terminal connected to the ground node; and

the second stacked gate device comprises one or more second finger structures arranged in parallel, with each second finger structure comprising a second number of field-effect transistors connected in series.

5 . The integrated circuit of claim 4 , wherein the first number is greater than the second number.

6 . The integrated circuit of claim 5 , wherein the field-effect transistors within the first stacked gate device and the second stacked gate device have a substantially equal threshold voltage.

7 . The integrated circuit of claim 6 , wherein:

the trimming circuit further comprises:

a plurality of buffer circuits, each buffer circuit configured to be supplied with a voltage at the first node and a ground voltage,

wherein each of the trimming stacked gate devices is controlled by a respective bit of a trimming code signal through a respective one of the buffer circuits.

8 . The integrated circuit of claim 7 , wherein each of the trimming stacked gate devices comprises a different number of finger structures in powers of 2, and each finger structure within the trimming stacked gate devices comprises the second number of field-effect transistors connected in series.

9 . The integrated circuit of claim 7 , wherein each of the trimming stacked gate devices comprises an equal number of finger structures, and each finger structure within the trimming stacked gate devices comprises the second number of field-effect transistors connected in series.

10 . The integrated circuit of claim 7 , wherein in response to the respective bit of a specific trimming stacked gate device being in a first logic state, the reference voltage is provided to a gate terminal of the specific trimming stacked gate device through the respective buffer circuit, enabling the specific trimming stacked gate device to couple to the second stacked gate device in parallel.

11 . The integrated circuit of claim 10 , wherein in response to the respective bit of the specific trimming stacked gate device being in a second logic state complementary to the first logic state, the ground voltage is provided to the gate terminal of the specific trimming stacked gate device through the respective buffer circuit, disabling the specific trimming stacked gate device from coupling to the second stacked gate device in parallel.

12 . The integrated circuit of claim 7 , further comprising: a third temperature-sensitive device, coupled between a power supply voltage and the first node, and configured to generate a third bias current, which monotonically decreases with the absolute temperature, flowing through the third temperature-sensitive device and the first temperature-sensitive device.

13 . The integrated circuit of claim 12 , wherein the third temperature-sensitive device comprises a third stacked gate device having a gate terminal and a first terminal connected to the power supply voltage, and a second terminal connected to the first node, and

the third stacked gate device comprises one or more third finger structures arranged in parallel, with each third finger structure comprising the first number of field-effect transistors connected in series.

14 . An integrated circuit, comprising:

a first temperature-sensitive device;

a second temperature-sensitive device, coupled to the first temperature-sensitive device through a resistor, and configured to function as a first voltage source varying with an absolute temperature of the integrated circuit, and operate in conjunction with the first temperature-sensitive device to function as a second voltage source varying with the absolute temperature of the integrated circuit,

wherein the second temperature-sensitive device is further configured to compensate the first voltage source with the second voltage source to generate a reference voltage at an output terminal of the integrated circuit; and

a trimming circuit comprising a plurality of trimming stacked gate devices, and configured to adjust a number of the trimming stacked gate devices that are coupled in parallel with the second temperature-sensitive device.

15 . The integrated circuit of claim 14 , wherein a first voltage provided by the first voltage source is complementary to the absolute temperature of the integrated circuit, and a second voltage provided by the second voltage source is proportional to the absolute temperature.

16 . The integrated circuit of claim 15 , wherein the first temperature-sensitive device is configured to generate a third voltage across a first node and a ground node, and cause a bias current to flow from the output terminal of the integrated circuit to the ground node through the resistor and the second temperature-sensitive device.

17 . The integrated circuit of claim 16 , wherein the bias current is equal to a voltage difference between the reference voltage and the third voltage divided by a resistance of the resistor.

18 . The integrated circuit of claim 17 , wherein the first temperature-sensitive device comprises a first stacked gate device having a first number of first field-effect transistors connected in series, the second temperature-sensitive device comprises a second stacked gate device having a second number of second field-effect transistors connected in series, and the second number is greater than the first number; and

the trimming circuit further comprises a plurality of buffer circuits, wherein each of the trimming stacked gate devices is controlled by a respective bit of a trimming code signal through a respective one of the buffer circuits.

19 . A method, comprising:

providing an integrated circuit comprising a first temperature-sensitive device and a second temperature-sensitive device;

generating a bias current using a first voltage across the first temperature-sensitive device and a second voltage across the second temperature-sensitive device, wherein the bias current flows from an output terminal of the integrated circuit through a resistor and the first temperature-sensitive device;

generating a reference voltage at the output terminal of the integrated circuit according to the second voltage and the bias current; and

adjusting a number of trimming stacked gate devices coupled in parallel with the second temperature-sensitive device,

wherein the first voltage and the second voltage monotonically decrease as an absolute temperature of the integrated circuit increases, and the bias current monotonically increases as the absolute temperature increases.

20 . The method of claim 19 , wherein a decrement of the first voltage in accordance with an increment of the absolute temperature is smaller than that of the second voltage in accordance with the increment of the absolute temperature.