IP Library › Granted Patent US 12687881
Granted Patent B2
US 12687881 · App. 18/813,588 · Granted Jul 21, 2026

Timer

Inventor: Patrick Arnould (Voreppe, FR)
Assignee: STMicroelectronics International N.V.
G06F1/08
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Quick Facts
Patent No.
US 12687881
App. No.
18/813,588
Granted
Jul 21, 2026
Kind
B2
Abstract

Provided is a circuit for managing a first clock signal clocking a timer adapted to being controlled by a processor clocked by a second clock signal. When the processor is off, the first clock signal is equal to a third clock signal having a frequency lower than the frequency of the second clock signal. When the processor is on, the first clock signal is equal to a fourth signal having a rising edge at each rising edge of the second clock signal directly following a rising edge of the third clock signal.

Claims (40)

1 . A circuit, comprising:

an output configured to output a first clock signal clocking a timer, the timer being configured to be controlled by a processor clocked by a second clock signal, wherein:

in response to said processor being off, the first clock signal is the same as a third clock signal having a frequency that is lower than a frequency of said second clock signal; and

in response to said processor being on, the first clock signal is the same as a fourth signal having a rising edge at each rising edge of the second clock signal directly following a rising edge of said third clock signal.

2 . The circuit according to claim 1 , comprising:

a first circuit configured to generate said fourth signal.

3 . The circuit according to claim 1 , comprising:

a second circuit configured to generate a fifth signal having a rising edge at each rising edge of said second clock signal directly following a falling edge of said third clock signal.

4 . The circuit according to claim 3 , comprising:

a third circuit for managing a state of said processor.

5 . The circuit according to claim 4 , wherein the third circuit is configured to output a signal for controlling the state of said processor clocked by said fifth signal.

6 . The circuit according to claim 1 , wherein the frequency of said second clock signal is in a range from 60 MHz to 10 GHz.

7 . The circuit according to claim 1 , wherein the frequency of said third clock signal is in a range from 1 kHz to 100 kHz.

8 . A timer, comprising:

a circuit, including:

an output configured to output a first clock signal clocking a timer, the timer being configured to be controlled by a processor clocked by a second clock signal, wherein:

in response to said processor being off, the first clock signal is the same as a third clock signal having a frequency that is lower than a frequency of said second clock signal; and

in response to said processor being on, the first clock signal is the same as a fourth signal having a rising edge at each rising edge of the second clock signal directly following a rising edge of said third clock signal.

9 . The timer according to claim 8 , comprising:

a core configured to be clocked by said first clock signal.

10 . An electronic device, comprising the timer according to claim 9 .

11 . The electronic device according to claim 10 , comprising said processor.

12 . The timer according to claim 8 , comprising:

registers configured to be clocked by said second clock signal.

13 . The timer according to claim 8 , comprising:

a first circuit configured to generate said fourth signal.

14 . The timer according to claim 8 , comprising:

a second circuit configured to generate a fifth signal having a rising edge at each rising edge of said second clock signal directly following a falling edge of said third clock signal.

15 . The timer according to claim 14 , comprising:

a third circuit for managing a state of said processor.

16 . The timer according to claim 15 , wherein the third circuit is configured to output a signal for controlling the state of said processor clocked by said fifth signal.

17 . The timer according to claim 8 , wherein the frequency of said second clock signal is in a range from 60 MHz to 10 GHz.

18 . A method, comprising:

outputting, by a circuit, a first clock signal that clocks a timer, the timer being configured to be controlled by a processor clocked by a second clock signal, wherein:

in response to said processor being off, the first clock signal is the same as a third clock signal having a frequency that is lower than a frequency of said second clock signal; and

in response to said processor being on, the first clock signal is the same as a fourth signal having a rising edge at each rising edge of the second clock signal directly following a rising edge of said third clock signal.

19 . The method according to claim 18 , comprising:

generating, by a first circuit, said fourth signal.

20 . The method according to claim 18 , comprising:

generating, by a second circuit, a fifth signal having a rising edge at each rising edge of said second clock signal directly following a falling edge of said third clock signal.