IP Library › Granted Patent US 12687882

Granted Patent B2

US 12687882 · App. 18/659,991 · Granted Jul 21, 2026

Latency synchronization

Inventor: Martin Brox (Munich, DE)

Assignee: Micron Technology, Inc.

G06F1/12

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Quick Facts

Patent No.: US 12687882
App. No.: 18/659,991
Granted: Jul 21, 2026
Kind: B2

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Abstract

Methods, systems, and devices for latency synchronization are described. A memory device may receive a data clock signal having a first rate and may generate a second clock signal having a second rate based on the data clock signal. A sampler may sample a first command signal indicating a command, where the second clock signal includes a first delay. A synchronizer may receive a second command signal from the sampler and a third clock signal from the sampler, where the second command signal and the third clock signal include a second delay. The synchronizer may synchronize a first timing of the second clock signal with a second timing of the third clock signal based on receiving the second command signal and the third clock signal and may output a signal including the second command signal and a synchronized clock signal having the second rate based on the synchronization.

Claims (64)

1 . A method, comprising:

receiving, at a memory device, a data clock signal having a first rate;

generating, at the memory device, a second clock signal having a second rate based at least in part on the data clock signal;

sampling, at a sampler, a first command signal indicating a command, wherein the sampling is performed using the second clock signal that includes a first delay associated with communicating the second clock signal to the sampler;

receiving, at a synchronizer of the memory device, a second command signal output by the sampler and a third clock signal output by the sampler, wherein the second command signal and the third clock signal include a second delay associated with communicating signals between the sampler and the synchronizer;

synchronizing, at the synchronizer, a first timing of the second clock signal with a second timing of the third clock signal based at least in part on receiving the second command signal and the third clock signal; and

outputting, by the synchronizer, a signal comprising the second command signal and a synchronized clock signal having the second rate based at least in part on the synchronization.

2 . The method of claim 1 , further comprising:

receiving, at a first input of the synchronizer, a first reset command signal;

resetting an output counter of the synchronizer based at least in part on receiving the first reset command signal at the first input;

receiving, at a second input of the synchronizer, the first reset command signal, wherein the first reset command signal at the second input includes at least the first delay and the second delay relative to the first reset command signal at the first input; and

resetting an input counter of the synchronizer based at least in part on receiving the first reset command signal at the second input.

3 . The method of claim 1 , further comprising:

detecting that each memory bank associated with the memory device is closed; and

powering down the synchronizer based at least in part on the detecting.

4 . The method of claim 1 , wherein the first timing of the second clock signal and the second timing of the third clock signal differ by a time duration that is based at least in part on the first delay and the second delay.

5 . The method of claim 2 , further comprising:

generating, at the sampler, a second reset command signal;

receiving, at a flip-flop of the memory device and from the sampler, the second reset command signal; and

generating, at the flip-flop, the first reset command signal based at least in part on the second reset command signal, wherein receiving the first reset command signal at the first input of the synchronizer and the second input of the synchronizer is based at least in part on generating the first reset command signal at the flip-flop.

6 . The method of claim 2 , wherein:

the first reset command signal at the second input further includes a third delay relative to the first reset command signal at the first input, and

the third delay is associated with a time duration between the sampler receiving the second clock signal and outputting the third clock signal.

7 . The method of claim 4 , wherein:

the time duration is further based at least in part on a third delay, and

the third delay is associated with a second time duration between the sampler receiving the second clock signal and outputting the third clock signal.

8 . An apparatus, comprising:

a receiver configured to receive a data clock signal having a first rate and to generate a second clock signal having a second rate based at least in part on the data clock signal;

a sampler configured to sample a first command/address signal, wherein the sampler is configured to perform the sampling using the second clock signal that includes a first delay associated with communicating the second clock signal to the sampler; and

a synchronizer configured to:

receive a second command/address signal output by the sampler and a third clock signal output by the sampler, wherein the second command/address signal and the third clock signal include a second delay associated with communicating signals between the sampler and the synchronizer;

synchronize a first timing of the second clock signal with a second timing of the third clock signal based at least in part on receiving the second command/address signal and the third clock signal; and

output a signal comprising the second command/address signal and a synchronized clock signal having the second rate based at least in part on the synchronization.

9 . The apparatus of claim 8 , wherein the synchronizer is configured to receive a first reset command signal at a first input of the synchronizer and to receive the first reset command signal at a second input of the synchronizer, wherein the first reset command signal at the second input includes at least the first delay and the second delay relative to the first reset command signal at the first input, the synchronizer comprising:

an output counter configured to be reset based at least in part on the synchronizer receiving the first reset command signal at the first input; and

an input counter of the synchronizer configured to be reset based at least in part on receiving the first reset command signal at the second input.

10 . The apparatus of claim 8 , wherein the apparatus is further configured to:

detect that each memory bank is closed; and

power down the synchronizer based at least in part on the detecting.

11 . The apparatus of claim 8 , wherein the first timing of the second clock signal and the second timing of the third clock signal differ by a time duration based at least in part on the first delay and the second delay.

12 . The apparatus of claim 9 , wherein the apparatus further comprises:

a flip-flop configured to receive a second reset command signal from the sampler and to generate the first reset command signal based at least in part on the second reset command signal, wherein the synchronizer is configured to receive the first reset command signal at the first input and the second input based at least in part on the first reset command signal.

13 . The apparatus of claim 9 , wherein:

the first reset command signal at the second input further includes a third delay relative to the first reset command signal at the first input, and

the third delay is associated with a time duration between the sampler receiving the second clock signal and outputting the third clock signal.

14 . The apparatus of claim 11 , wherein:

the time duration is further based at least in part on a third delay, and

the third delay is associated with a second time duration between the sampler receiving the second clock signal and outputting the third clock signal.

15 . A memory device, comprising:

a synchronizer configured to:

receive a second clock signal having a second rate based at least in part on a data clock signal that has a first rate;

receive a command signal output by a sampler and a third clock signal output by the sampler, wherein the command signal and the third clock signal include a delay associated with communicating signals between the sampler and the synchronizer;

synchronize a first timing of the second clock signal with a second timing of the third clock signal based at least in part on receiving the command signal and the third clock signal; and

output a signal comprising the command signal and a synchronized clock signal having the second rate based at least in part on the synchronization.

16 . The memory device of claim 15 , wherein the synchronizer is further configured to:

receive, at a first input of the synchronizer, a first reset command signal;

reset an output counter of the synchronizer based at least in part on receiving the first reset command signal at the first input;

receive, at a second input of the synchronizer, the first reset command signal, wherein the first reset command signal at the second input includes at least the delay relative to the first reset command signal at the first input; and

reset an input counter of the synchronizer based at least in part on receiving the first reset command signal at the second input.

17 . The memory device of claim 15 , wherein the synchronizer is further configured to:

power down when each memory bank associated with the memory device is closed.

18 . The memory device of claim 15 , wherein the first timing of the second clock signal and the second timing of the third clock signal differ by a time duration based at least in part on the delay.

19 . The memory device of claim 16 , wherein the first reset command signal at the second input further includes a second delay associated with communicating the second clock signal to the sampler and a third delay associated with a time duration between the sampler receiving the second clock signal and outputting the third clock signal.

20 . The memory device of claim 18 , wherein the time duration is further based at least in part on a second delay associated with communicating the second clock signal to the sampler and a third delay associated with a second time duration between the sampler receiving the second clock signal and outputting the third clock signal.