IP Library Granted Patent US 12687904
Granted Patent B2
US 12687904 · App. 18/447,576 · Granted Jul 21, 2026

Integrated circuit capable of performing dynamic voltage and frequency scaling operation based on workload and operating method thereof

Inventor: Gyehyung Kim (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F1/26
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Quick Facts
Patent No.
US 12687904
App. No.
18/447,576
Granted
Jul 21, 2026
Kind
B2
Abstract

Provided are an integrated circuit capable of classifying a workload of a core based on monitored data and performing a dynamic voltage and frequency scaling (DVFS) operation based on the classified workload, and an operating method of the integrated circuit. The integrated circuit includes at least one core, a shared buffer which receives a request from the at least one core, access an external memory according to the request, and receive a response from the external memory, a monitor which monitors the shared buffer to obtain a buffer capacity of the shared buffer and a response waiting time, and a DVFS controller configured to classify a workload of the at least one core.

Claims (59)

1 . A device comprising at least one integrated circuit, the integrated circuit comprising:

a plurality of cores configured to process an instruction according to a voltage-frequency level;

a shared buffer, comprising a plurality of blocks, configured to receive a request including data designating a certain block among the plurality of blocks from a first core of the plurality of cores, access an external memory according to the request, and receive a response from the external memory, wherein each of the plurality of blocks is configured to access a corresponding designated region among a plurality of regions of the external memory;

a monitor configured to monitor the shared buffer to obtain a buffer capacity of the shared buffer, the buffer capacity corresponding to a number of respective ones of the plurality of blocks each using a threshold capacity being greater than or equal to a threshold number among the plurality of blocks, a response waiting time for the response received from the external memory, and an identifier of the first core; and

a dynamic voltage and frequency scaling (DVFS) controller configured to receive, from the monitor, the buffer capacity, the response waiting time and the identifier, and to identify the first core according to the identifier and classify a workload of the first core based on the buffer capacity and the response waiting time, and determine a scaling factor for the voltage-frequency level of the first core based on the classified workload.

2 . The device of claim 1 , wherein

the DVFS controller is further configured to classify the workload of the first core as a first workload or a second workload based on the buffer capacity and the response waiting time, and

the first workload includes more requests for accessing the external memory than the second workload.

3 . The device of claim 2 , wherein, based on the buffer capacity indicating a full state, and the response waiting time is longer than a threshold time, the DVFS controller is further configured to classify the workload of the first core as the first workload.

4 . The device of claim 3 , wherein

the buffer capacity that is in the full state indicates a state in which a number of blocks using the threshold capacity or more, among the plurality of blocks, is greater than or equal to the threshold number.

5 . The device of claim 2 , further comprising a temperature sensor configured to measure a temperature of the first core and transmit the measured temperature to the DVFS controller,

wherein, based on the buffer capacity not being full or the response waiting time being shorter than a threshold time, the DVFS controller is further configured to classify the workload of the first core having the measured temperature greater than or equal to a threshold temperature as the second workload.

6 . The device of claim 2 , wherein, based on the classified workload being the first workload, the DVFS controller is further configured to determine the scaling factor such that the voltage-frequency level of the first core decreases to adjust a number of requests transmitted from the first core to the shared buffer.

7 . The device of claim 1 , wherein the DVFS controller further comprises:

a memory configured to store training data including the buffer capacity, the response waiting time, and the scaling factor; and

a processor configured to

train an artificial neural network model by using the training data,

determine the scaling factor corresponding to the buffer capacity and the response waiting time received from the monitor, by using the trained artificial neural network model after the training is completed.

8 . The device of claim 7 , wherein

the training data comprises an address of the external memory included in the request, and

the processor is further configured to, after the training is completed, receive the address from the monitor and determine the scaling factor corresponding to the address.

9 . The device of claim 1 , wherein each of the plurality of blocks is configured to access the corresponding designated region only from the plurality of regions of the external memory.

10 . An operating method of an integrated circuit, the operating method comprising:

monitoring a shared buffer which comprises a plurality of blocks and obtaining a buffer capacity of the shared buffer, a response waiting time for a response received from an external memory, and an identifier of a first core of a plurality of cores, wherein the shared buffer receives a request including data designating a certain block among the plurality of blocks from the first core, and wherein each of the plurality of blocks is configured to access a corresponding designated region among a plurality of regions of the external memory, the buffer capacity corresponding to a number of respective ones of the plurality of blocks each using a threshold capacity being greater than or equal to a threshold number among the plurality of blocks;

classifying a workload of the first core based on the buffer capacity and the response waiting time; and

determining a scaling factor for a voltage-frequency level of the first core based on the classified workload of the first core.

11 . The operating method of claim 10 , wherein

the classifying of the workload of the first core based on the buffer capacity and the response waiting time comprises classifying the workload of the first core as a first workload or a second workload, and

the first workload includes more requests for accessing the external memory than the second workload.

12 . The operating method of claim 11 , wherein the classifying of the workload of the first core as the first workload or the second workload further comprises, based on the buffer capacity indicating a full state, and the response waiting time being longer than a threshold time, classifying the workload of the first core as the first workload.

13 . The operating method of claim 11 , wherein the determining of the scaling factor for the voltage-frequency level of the first core based on the classified workload of the first core further comprises, based on the classified workload being the first workload, determining the scaling factor such that the voltage-frequency level of the first core decreases to adjust a number of requests transmitted from the first core to the shared buffer.

14 . A computing system comprising:

a processor comprising a plurality of cores;

at least one memory;

a bus connecting the processor to the at least one memory;

a dynamic voltage and frequency scaling (DVFS) controller configured to identify a first core of the plurality of cores according to an identifier of the first core, and classify a workload of the first core based on a buffer capacity of a shared buffer and a response waiting time for a response received from the bus, determine a scaling factor based on the classified workload, and generate a voltage control signal and a clock control signal based on the determined scaling factor, the shared buffer comprises a plurality of blocks, wherein each of the plurality of blocks is configured to access a corresponding designated region among a plurality of regions of the at least one memory, the buffer capacity corresponding to a number of respective ones of the plurality of blocks each using a threshold capacity being greater than or equal to a threshold number among the plurality of blocks;

a power management unit configured to adjust an amplitude of a power supply voltage provided to the first core in response to the voltage control signal; and

a clock management unit configured to adjust a frequency of a clock signal provided to the first core, in response to the clock control signal, wherein

each of the plurality of cores configured to process an instruction according to the amplitude of the power supply voltage and the frequency of the clock signal;

the processor further comprising

the shared buffer configured to receive a request including data designating a certain block among the plurality of blocks from the first core of the plurality of cores, access the bus according to the request, and receive the response from the bus; and

a monitor configured to monitor the shared buffer to obtain the buffer capacity, the response waiting time and the identifier of the first core.

15 . The computing system of claim 14 ,

wherein the DVFS controller further comprises:

a DVFS governor module configured to determine the scaling factor;

a power management unit driver configured to generate a power supply voltage control signal based on the determined scaling factor; and

a clock management unit driver configured to generate a frequency control signal based on the determined scaling factor.

16 . The computing system of claim 14 , wherein

the DVFS controller is further configured to classify the workload of the first core as a first workload or a second workload based on the buffer capacity and the response waiting time, and

the first workload includes more requests for accessing the at least one memory than the second workload.

17 . The computing system of claim 16 , wherein

based on the response waiting time being longer than a threshold time, the DVFS controller is further configured to classify the workload of the first core as the first workload.

18 . The computing system of claim 16 , wherein, based on the classified workload being the first workload, the DVFS controller is further configured to determine the scaling factor such that the amplitude of the power supply voltage and the frequency of the clock signal decreases to adjust a number of requests transmitted from the first core to the shared buffer.

19 . The computing system of claim 15 , wherein

the DVFS controller further comprises:

a memory configured to store training data including the buffer capacity, the response waiting time, and the scaling factor; and

a processor configured to train an artificial neural network model by using the training data, and

the processor is further configured to, after the training is completed, determine the scaling factor corresponding to the buffer capacity and the response waiting time received from the monitor, by using the trained artificial neural network model.