IP Library Granted Patent US 12687910
Granted Patent B2
US 12687910 · App. 18/215,034 · Granted Jul 21, 2026

Usage scenario based monitoring and adjustment

Inventors: Zhongsheng Wang (Portland, OR); James Hermerding, II (Vancouver, WA)
Assignee: Intel Corporation
G06F1/3206G06F1/206G06F1/324G06F9/5083G06F15/76G06F15/7807G06F2015/761
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Quick Facts
Patent No.
US 12687910
App. No.
18/215,034
Granted
Jul 21, 2026
Kind
B2
Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to monitor and manage usage of resources on a computing platform. An example apparatus includes a processor and a subsystem. The example processor includes a modified operating system, the operating system modified to monitor application execution via the processor to determine a usage scenario for the apparatus. The example processor includes an index generator to generate a system usage scenario index quantifying a snapshot of the usage scenario for the processor and the subsystem of the apparatus. The example processor includes a rebalancer to reallocate resources of at least one of the processor or the subsystem based on the system usage scenario index.

Claims (29)

1 . An apparatus comprising:

memory circuitry;

instructions;

a graphics processing unit (GPU) on a discrete graphics card;

processor circuitry in at least one of i) the GPU or ii) a central processing unit (CPU) separate from the discrete graphics card; and

a system to, during execution of an application by at least one of the CPU or the GPU, monitor a balance of utilization between the CPU and the GPU on a per-frame basis, the balance of utilization including a first utilization associated with the CPU and a second utilization associated with the GPU,

for each frame, the processor circuitry to execute the instructions to:

when the first utilization is greater than the second utilization, balance a power allocation between the GPU and the CPU by increasing a first power budget of the CPU and decreasing a second power budget of the GPU; and

when the second utilization is greater than the first utilization, balance the power allocation between the GPU and the CPU by increasing the second power budget of the GPU and decreasing the first power budget of the CPU.

2 . The apparatus of claim 1 , wherein the processor circuitry is to execute the instructions at least once per frame.

3 . The apparatus of claim 1 , wherein the application is a graphics rendering application.

4 . The apparatus of claim 1 , wherein execution of the application by the at least one of the GPU or the CPU defines a system usage.

5 . The apparatus of claim 1 , wherein the system includes an operating system.

6 . The apparatus of claim 1 , further including the CPU.

7 . The apparatus of claim 1 , further including a GPU memory.

8 . The apparatus of claim 1 , wherein the at least one of the GPU or the CPU is triggered to rebalance after at least one of the first utilization or the second utilization satisfying a threshold.

9 . The apparatus of claim 1 , wherein the frame is a video frame.

10 . At least one non-transitory computer readable storage medium comprising instructions to cause processor circuitry to at least:

during execution of an application by at least one of a central processing unit (CPU) or a graphics processing unit (GPU), monitor a balance of utilization between the CPU and the GPU on a per-frame basis, the balance of utilization including a first utilization associated with the CPU and a second utilization associated with the GPU; and

for each frame, (a) when the first utilization is greater than the second utilization, balance a power allocation between the GPU and the CPU by increasing a first power budget of the CPU and decreasing a second power budget of the GPU, and (b) when the second utilization is greater than the first utilization, balance the power allocation between the GPU and the CPU by increasing the second power budget of the GPU and decreasing the first power budget of the CPU.

11 . The at least one non-transitory computer readable storage medium of claim 10 , wherein the instructions cause the processor circuitry to continue monitoring utilization of the GPU and the CPU.

12 . The at least one non-transitory computer readable storage medium of claim 11 , wherein the instructions cause the processor circuitry to execute the instructions at least once per frame.

13 . The at least one non-transitory computer readable storage medium of claim 10 , wherein the application is a graphics rendering application.

14 . The at least one non-transitory computer readable storage medium of claim 10 , wherein execution of the application by at least one of the GPU or the CPU defines a system usage.

15 . The at least one non-transitory computer readable storage medium of claim 10 , wherein the instructions cause the processor circuitry to monitor the first utilization and the second utilization via an operating system.

16 . The at least one non-transitory computer readable storage medium of claim 10 , wherein the instructions cause the processor circuitry to trigger rebalancing when at least one of the first utilization or the second utilization exceeds a threshold.

17 . The at least one non-transitory computer readable storage medium of claim 10 , wherein the instructions cause the processor circuitry to monitor a third utilization of a GPU memory.

18 . The at least one non-transitory computer readable storage medium of claim 10 , wherein the processor circuitry is implemented by the CPU.

19 . The at least one non-transitory computer readable storage medium of claim 10 , wherein the frame is a video frame.