Fractional frequency divider and flash memory controller
The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
1 . A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module comprises at least one flash memory chip, and the flash memory controller comprising:
a memory, for storing a program code;
a microprocessor, configured to execute the program code to access the flash memory module; and
a control logic, configured to control the flash memory module, wherein the control logic comprises:
a clock signal generator, configured to generate a clock signal and an input clock signal;
a fractional frequency divider, configured to receive the input clock signal to generate an output clock signal; and
a digital circuit;
wherein when the flash memory controller operates in a normal mode, the fractional frequency divider does not mask any part of the input clock signal to generate the output clock signal, and the digital circuit works by using the output clock signal which is equal to the input clock signal; and when the flash memory controller operates in a power saving mode, the fractional frequency divider masks part of the input clock signal to generate the output clock signal, and the digital circuit works by using the output clock signal.
2 . The flash memory controller of claim 1 , wherein the digital circuit is an encoder or a decoder.
3 . The flash memory controller of claim 1 , wherein the digital circuit is a randomizer or a de-randomizer.
4 . A memory device, comprising:
a flash memory module, wherein the flash memory module comprises at least one flash memory chip;
a flash memory controller, configured to access the flash memory module, wherein a control logic within the flash memory controller comprises:
a clock signal generator, configured to generate a clock signal and an input clock signal;
a fractional frequency divider, configured to receive the input clock signal to generate an output clock signal;
a digital circuit;
wherein when the flash memory controller operates in a normal mode, the fractional frequency divider does not mask any part of the input clock signal to generate the output clock signal, and the digital circuit works by using the output clock signal which is equal to the input clock signal; and when the flash memory controller operates in a power saving mode, the fractional frequency divider masks part of the input clock signal to generate the output clock signal, and the digital circuit works by using the output clock signal.
5 . The memory device of claim 4 , wherein the digital circuit is an encoder or a decoder.
6 . The memory device of claim 4 , wherein the digital circuit is a randomizer or a de-randomizer.