IP Library Granted Patent US 12687966
Granted Patent B2
US 12687966 · App. 19/041,987 · Granted Jul 21, 2026

Adjusted programming associated with read errors

Inventors: Saswati Das (Milpitas, CA); Nian Niles Yang (Mountain View, CA); Srinivas Yelisetti (Fremont, CA)
Assignee: Microchip Technology Incorporated
G06F3/0614G06F3/0659G06F3/0679G11C16/10G11C16/26G11C16/3459
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Quick Facts
Patent No.
US 12687966
App. No.
19/041,987
Granted
Jul 21, 2026
Kind
B2
Abstract

In some implementations, a storage device may perform a read operation using a first read voltage. The storage device may identify a read error associated with the read operation. The storage device may identify a difference between the first read voltage and a second read voltage, the second read voltage associated with a reduced raw bit error rate (RBER). The storage device may perform a write operation using a program verify voltage that is based on the difference.

Claims (50)

1 . A method performed by a storage device, the method comprising:

performing a read operation using a first read voltage;

identifying a read error associated with the read operation;

identifying a difference between the first read voltage and a second read voltage, the second read voltage associated with a reduced raw bit error rate (RBER); and

performing a write operation using a program verify voltage that is based on the difference.

2 . The method of claim 1 , wherein the difference between the first read voltage and the second read voltage comprises an amount of a shift and a direction of the shift.

3 . The method of claim 1 , comprising:

identifying, based at least in part on performing error correction associated with the read error, the second read voltage associated with the reduced raw bit error rate (RBER).

4 . The method of claim 1 , comprising:

moving data associated with the read operation to a new block associated with a different physical location of the storage device.

5 . The method of claim 1 , comprising:

storing, in metadata of a virtual block associated with the read operation, an indication of the difference.

6 . The method of claim 1 , comprising:

adjusting a program voltage based on the program verify voltage.

7 . The method of claim 6 , comprising:

applying the program voltage, after the adjusting, to a virtual block associated with the read operation, or

applying the program voltage, after the adjusting, to one or more physical blocks associated with the virtual block.

8 . The method of claim 1 , wherein performing the write operation using the program verify voltage that is based on the difference comprises:

using the program verify voltage during the write operation based on the write operation being associated with a same page type of a same logical unit number (LUN) of a same virtual block as the read operation.

9 . The method of claim 1 , wherein the read operation is associated with a page type and a logical unit number (LUN) of a virtual block, and

wherein the write operation is associated with the page type and the LUN.

10 . The method of claim 1 , wherein the read operation is associated with a page type and a logical unit number (LUN) of a virtual block, and

wherein the program verify voltage is applied to the page type and the LUN for one or more subsequent program operations.

11 . The method of claim 1 , wherein the program verify voltage is offset from a default program verify voltage.

12 . The method of claim 1 , comprising:

adjusting a program step voltage based at least in part on the program verify voltage.

13 . A system comprising:

a controller, of a non-volatile memory device, to:

perform a read operation using a first read voltage;

identify a read error associated with the read operation;

identify a difference between the first read voltage and a second read voltage, the second read voltage associated with a reduced raw bit error rate (RBER);

adjust a program verify voltage based at least in part on the difference; and

perform a write operation using the program verify voltage that is based at least in part on the difference.

14 . The system of claim 13 , wherein the difference comprises an amount of a shift and a direction of the shift from the first read voltage to the second read voltage.

15 . The system of claim 13 , wherein the controller is to:

identify, based at least in part on performing error correction associated with the read operation, the second read voltage associated with the reduced RBER.

16 . The system of claim 13 , wherein the controller is to:

store an indication of the difference in metadata of a virtual block associated with the read operation.

17 . A computer program product comprising:

one or more non-transitory computer readable storage media, and program instructions collectively stored on the one or more non-transitory computer readable storage media, the program instructions comprising:

program instructions to perform a read operation using a first read voltage;

program instructions to identify a read error associated with the read operation;

program instructions to perform the read operation using a second read voltage different than the first read voltage;

program instructions to identify a difference between the first read voltage and the second read voltage, the second read voltage being associated with a reduced raw bit error rate (RBER), wherein the difference comprises an amount of a shift from the first read voltage to the second read voltage and a direction of the shift from the first read voltage to the second read voltage; and

program instructions to perform a write operation using a program verify voltage that is based on the difference.

18 . The computer program product of claim 17 , wherein the program instructions comprise:

program instructions to store an indication of the difference in metadata of a virtual block associated with the read operation.

19 . The computer program product of claim 17 , wherein the read operation is associated with a page type and a logical unit number (LUN) of a virtual block, and

wherein the write operation is associated with the page type and the LUN.

20 . The computer program product of claim 17 , wherein the program verify voltage is offset from a default program verify voltage.