Verify failbit count circuit, memory device, memory system and method

1 . A memory device, comprising:

a memory array; and

a count circuit coupled to the memory array, wherein the count circuit comprises:

a verify standard selector configured to output a verify standard signal;

a bit counter circuit coupled to the verify standard selector and configured to receive the verify standard signal and output at least one comparison result, wherein the bit counter circuit comprises:

a highest bit counter coupled to the verify standard selector and configured to receive the verify standard signal and output a first enable signal and a first comparison result of the at least one comparison result, and

a lowest bit counter coupled to the highest bit counter and configured to receive the first enable signal and output a second enable signal and a second comparison result of the at least one comparison result; and

a code converter coupled to the bit counter circuit.

2 . The memory device of claim 1 , wherein the verify standard selector comprises at least one inverter.

3 . The memory device of claim 2 , wherein both an input terminal and an output terminal of the verify standard selector are coupled to the bit counter circuit.

4 . The memory device of claim 2 , wherein the verify standard selector is configured to select one from at least two verify standards with different magnitudes as the verify standard signal.

5 . The memory device of claim 1 , wherein the bit counter circuit further comprises:

at least one intermediate bit counter, a first intermediate bit counter of the at least one intermediate bit counter being coupled to the lowest bit counter and configured to receive the second enable signal and output a third enable signal and a third comparison result of the at least one comparison result.

6 . The memory device of claim 5 , wherein the highest bit counter comprises:

a first comparator configured to receive the verify standard signal and a verify failbit signal and output the first comparison result; and

a first inverter coupled to the first comparator and configured to:

receive the first comparison result; and

output the first enable signal based on the first comparison result, the first enable signal being an inverse signal of the first comparison result.

7 . The memory device of claim 5 , wherein the lowest bit counter comprises:

a first control circuit coupled to the highest bit counter and configured to receive the first enable signal and control a switch between an enabled status and a disabled status of the lowest bit counter based on the first enable signal; and

a second comparator configured to:

receive a verify failbit signal and a first reference signal; and

output the second comparison result and the second enable signal, the second enable signal being in phase with the second comparison result.

8 . The memory device of claim 7 , wherein each of the at least one intermediate bit counter has a same structure as the lowest bit counter.

9 . The memory device of claim 5 , wherein intermediate bit counters are connected sequentially based on their respective reference signals from low to high.

10 . The memory device of claim 1 , further comprising:

an accumulator coupled to the code converter and configured to accumulate a plurality of binary codes obtained from the code converter.

11 . A method of operating a memory device, comprising:

selecting one from at least two verify standards with different magnitudes and outputting a verify standard signal;

in response to receiving the verify standard signal, outputting at least one comparison result, comprising:

comparing a verify failbit signal with the verify standard signal to generate a first comparison result,

outputting a first enable signal based on the first comparison result,

in response to the first enable signal, comparing the verify failbit signal with a first reference signal to generate a second comparison result, and

outputting a second enable signal based on the second comparison result; and

converting the at least one comparison result into a binary code.

12 . The method of claim 11 , further comprising accumulating a plurality of binary codes.

13 . The method of claim 11 , wherein in response to receiving the verify standard signal, outputting at least one comparison result further comprises:

in response to the second enable signal, comparing the verify failbit signal with a second reference signal to generate a third comparison result.

14 . A memory system, comprising:

a memory device, comprising:

a memory array; and

a count circuit coupled to the memory array, wherein the count circuit comprises:

a verify standard selector configured to output a verify standard signal;

a bit counter circuit coupled to the verify standard selector and configured to receive the verify standard signal and output at least one comparison result, wherein the bit counter circuit comprises:

a highest bit counter coupled to the verify standard selector and configured to receive the verify standard signal and output a first enable signal and a first comparison result of the at least one comparison result, and

a lowest bit counter coupled to the highest bit counter and configured to receive the first enable signal and output a second enable signal and a second comparison result of the at least one comparison result; and

a code converter coupled to the bit counter circuit; and

a memory controller coupled to the memory device and configured to control the memory device.

15 . The memory system of claim 14 , wherein the verify standard selector comprises at least one inverter.

16 . The memory system of claim 15 , wherein both an input terminal and an output terminal of the verify standard selector are coupled to the bit counter circuit.

17 . The memory system of claim 15 , wherein the verify standard selector is configured to select one from at least two verify standards with different magnitudes as the verify standard signal.

18 . The memory system of claim 14 , wherein the bit counter circuit further comprises:

at least one intermediate bit counter, a first intermediate bit counter of the at least one intermediate bit counter being coupled to the lowest bit counter and configured to receive the second enable signal and output a third enable signal and a third comparison result of the at least one comparison result.

19 . The memory system of claim 18 , wherein each of the at least one intermediate bit counter has a same structure as the lowest bit counter.

20 . The memory system of claim 14 , wherein the memory device further comprises an accumulator coupled to the code converter and configured to accumulate a plurality of binary codes obtained from the code converter.