Combined divide/square root processing circuitry and method
An apparatus comprises combined divide/square root processing circuitry to perform, in response to a divide instruction, a given radix-64 iteration of a radix-64 divide operation, and in response to a square root instruction, a given radix-64 iteration of a radix-64 square root operation; in which: the combined divide/square root processing circuitry comprises shared circuitry to generate at least one output value for the given radix-64 iteration on a same data path used for both the radix-64 divide operation and the radix-64 square root operation.
1 . An apparatus comprising:
combined divide/square root processing circuitry configured to perform, in response to a divide instruction, a given radix r iteration of a radix r divide operation, and in response to a square root instruction, a given radix r iteration of a radix r square root operation; in which:
the combined divide/square root processing circuitry comprises shared circuitry configured to generate at least one output value for the given radix r iteration on a same data path used for both the radix r divide operation and the radix r square root operation;
for both the radix-r divide operation and the radix-r square root operation, the combined divide/square root processing circuitry is configured to perform the given radix-r iteration by performing a plurality of radix-m sub-iterations in a same processing cycle, where m≤r;
the shared circuitry comprises shared on-the-fly conversion circuitry configured to perform, in a given radix-m sub-iteration, on-the-fly conversion to generate a partial result value in a non-redundant representation; and
in the given radix-m sub-iteration, the shared on-the-fly conversion circuitry is configured to select a position for inserting a next digit into the partial result value based on a mask value, for both the radix-r divide operation and the radix-r square root operation.
2 . The apparatus according to claim 1 , in which the combined divide/square root processing circuitry is configured to perform a same number of radix r iterations per processing cycle for both the radix r divide operation and the radix r square root operation.
3 . The apparatus according to claim 1 , in which m=8.
4 . The apparatus according to claim 1 , in which the shared circuitry comprises shared digit selection circuitry configured to select, in a given radix-m sub-iteration, a next radix-m digit for a divide result or a square root result, based on comparison of a previous remainder estimate with a set of comparison constants.
5 . The apparatus according to claim 4 , in which m<r and in a later radix-m sub-iteration of the given radix r iteration, the shared digit selection circuitry is configured to select the next radix-m digit based on the previous remainder estimate calculated in an earlier radix-m sub-iteration of the given radix r iteration.
6 . The apparatus according to claim 4 , in which a same set of comparator circuits is used to perform the comparison for both a given radix-m sub-iteration of the radix r divide operation and a given radix-m sub-iteration of the radix r square root operation.
7 . The apparatus according to claim 4 , in which the shared digit selection circuitry is configured to use different sets of comparison constants for the radix r divide operation and the radix r square root operation respectively.
8 . The apparatus according to claim 7 , in which the comparison constants compared with the previous remainder estimate for the radix r divide operation have at least one least significant bit set to 0 to pad the comparison constants for the radix r divide operation to a same width as the comparison constants compared with the previous remainder estimate for the radix r square root operation.
9 . The apparatus according to claim 1 , in which the shared circuitry comprises shared remainder update circuitry configured to adjust, in a given radix-m sub-iteration, a previous remainder value based on a remainder adjustment value to generate an updated remainder value in a redundant representation.
10 . The apparatus according to claim 9 , in which the shared circuitry comprises shared carry-save adding circuitry configured to perform a carry-save addition to generate the updated remainder value.
11 . The apparatus according to claim 9 , in which the shared remainder update circuitry comprises selection circuitry configured to select, as the remainder adjustment value:
a value derived from a divisor value, when performing the given radix-m sub-iteration as part of the radix r divide operation, and
a value derived from a partial root value depending on a sequence of previously selected radix-m root digits, when performing the given radix-m sub-iteration as part of the radix r square root operation.
12 . The apparatus according to claim 1 , in which the shared circuitry comprises shared remainder estimate circuitry configured to generate, in a given radix-m sub-iteration, an updated remainder estimate indicative of a non-redundant estimate of a portion of an updated remainder value generated in a redundant representation in the given radix-m sub-iteration of the radix r divide operation or the radix r square root operation.
13 . The apparatus according to claim 12 , in which m<r, and in a final radix-m sub-iteration of the given radix r iteration, the shared remainder estimate circuitry is configured to generate the updated remainder estimate in parallel with shared remainder update circuitry generating the updated remainder value.
14 . The apparatus according to claim 1 , in which the shared circuitry comprises one or more instances of replicated circuitry, each instance of replicated circuitry comprising:
two or more replicated circuit units configured to determine, in parallel with selection of a next radix-m digit for a divide result or a square root result, two or more candidate output values corresponding to different digits which are capable of being selected as the next radix-m digit, and
selection circuitry configured to select one of a plurality of candidate output values in response an indication of which of the different digits was selected as the next radix-m digit, the plurality of candidate output values including at least the two or more candidate output values generated by the two or more replicated circuit units.
15 . The apparatus according to claim 14 , in which at least one of the two or more replicated circuit units is a shared circuit unit shared between positive and negative digits of equal magnitude, the shared circuit unit is configured to output a shared candidate output value to the selection circuitry on a shared signal path, and the selection circuitry is configured to select the shared candidate output value from the shared signal path when the next radix-m digit is any of the positive and negative digits of equal magnitude.
16 . The apparatus according to claim 1 , in which the combined divide/square root processing circuitry comprises iterative divide/square root processing circuitry comprising signal paths to supply outputs of the given radix r iteration as inputs to the same iterative divide/square root processing circuitry for use in a further radix r iteration of the radix-r divide operation or the radix r square root operation.
17 . The apparatus according to claim 1 , comprising a pipelined divide/square root processing unit comprising:
a plurality of combined divide/square root iteration pipeline stages each comprising a respective instance of said combined divide/square root processing circuitry; and
signal paths configured to supply outputs of the given radix r iteration generated by the combined divide/square root processing circuitry in one divide/square root iteration pipeline stage as inputs to the combined divide/square root processing circuitry in a subsequent divide/square root iteration pipeline stage, for use in a further radix r iteration of the radix r divide operation or the radix r square root operation.
18 . The apparatus according to claim 1 , in which r=64.
19 . A data processing method comprising:
in response to a divide instruction or a square root instruction, performing a given radix-r iteration of a radix r divide operation or a given radix r iteration of a radix r square root operation using combined divide/square root processing circuitry;
in which:
the combined divide/square root processing circuitry comprises shared circuitry to generate at least one output value for the given radix r iteration on a same data path used for both the radix r divide operation and the radix r square root operation;
for both the radix-r divide operation and the radix-r square root operation, the combined divide/square root processing circuitry performs the given radix-r iteration by performing a plurality of radix-m sub-iterations in a same processing cycle, where m≤r;
the shared circuitry comprises shared on-the-fly conversion circuitry which performs, in a given radix-m sub-iteration, on-the-fly conversion to generate a partial result value in a non-redundant representation; and
in the given radix-m sub-iteration, the shared on-the-fly conversion circuitry is configured to select a position for inserting a next digit into the partial result value based on a mask value, for both the radix-r divide operation and the radix-r square root operation.
20 . A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:
combined divide/square root processing circuitry to perform, in response to a divide instruction, a given radix r iteration of a radix r divide operation, and in response to a square root instruction, a given radix r iteration of a radix r square root operation; in which:
the combined divide/square root processing circuitry comprises shared circuitry to generate at least one output value for the given radix r iteration on a same data path used for both the radix r divide operation and the radix r square root operation;
for both the radix-r divide operation and the radix-r square root operation, the combined divide/square root processing circuitry is configured to perform the given radix-r iteration by performing a plurality of radix-m sub-iterations in a same processing cycle, where m≤r;
the shared circuitry comprises shared on-the-fly conversion circuitry to perform, in a given radix-m sub-iteration, on-the-fly conversion to generate a partial result value in a non-redundant representation; and
in the given radix-m sub-iteration, the shared on-the-fly conversion circuitry is configured to select a position for inserting a next digit into the partial result value based on a mask value, for both the radix-r divide operation and the radix-r square root operation.