Processor controlled programmable logic device modification
Systems or methods of the present disclosure may provide a computing system that includes a processor and one or more implemented designs in one or more configurable circuits of a programmable logic fabric. The computing system also includes a memory coupled to the programmable logic fabric. The computing system further includes an accelerator that is located in-line between the one or more configurable circuits and the memory. The accelerator is defined using a low-level programming language. The processor is coupled to the accelerator and is configured to enable modification of the definition of the accelerator by converting a high-level programming language to the low-level programming language to change the way that the accelerator operates.
1 . A computing system, comprising:
memory configured to store data;
a programmable logic fabric coupled to the memory, wherein the programmable logic fabric is to implement an accelerator, wherein the memory is external to the programmable logic fabric; and
a processor coupled to the programmable logic fabric, wherein the processor is external to the programmable logic fabric that makes the memory available to the processor, and is configured to process and manipulate the stored data in the memory by accessing the memory based on snooping through the accelerator using coherency agents of a first protocol, wherein the coherency agents are configured to snoop inside the processor and the accelerator and enable the processor to modify a definition of the accelerator and snoop the memory using communications through the programmable logic fabric to provide a coherent interconnection between the memory and the processor through the programmable logic fabric, wherein the coherency agents of the first protocol are configured to snoop inside the programmable logic fabric via second coherency agents of a second protocol, wherein the second coherency agents of the second protocol are configured to coherently interconnect a second memory to the processor, and the processor is configured to modify the accelerator dynamically during a runtime of the computing system based at least in part on the coherency agents being configured to snoop inside the processor and the accelerator.
2 . The computing system of claim 1 , wherein the processor is configured to access the memory based on receiving instructions of a high-level programming language.
3 . The computing system of claim 1 , wherein the accelerator is defined using a Hardware Description Language (HDL).
4 . The computing system of claim 1 , wherein the accelerator is programmed using a Register Transfer Level description.
5 . The computing system of claim 1 , wherein the processor is configured to convert high-level programming language to a Hardware Description Language (HDL) using a compiler.
6 . The computing system of claim 1 , wherein the processor is configured to modify the definition of the accelerator to perform data encryption or data decryption based at least in part on the coherency agents being configured to snoop inside the processor and the accelerator.
7 . The computing system of claim 6 , wherein the accelerator comprises a plurality of selectable operation instructions defined for data encryption, wherein the processor is configured to select a selectable operation instruction of the plurality of selectable operation instructions to modify the definition of the accelerator.
8 . The computing system of claim 6 , wherein the accelerator comprises a plurality of selectable operation instructions defined for data decryption, wherein the processor is configured to select a selectable operation instruction of the plurality of selectable operation instructions to modify the definition of the accelerator.
9 . The computing system of claim 1 , wherein the processor is configured to modify the definition of the accelerator to perform data compression or data decompression based at least in part on the coherency agents being configured to snoop inside the processor and the accelerator.
10 . The computing system of claim 9 , wherein the accelerator comprises a plurality of selectable operation instructions defined for data compression, wherein the processor is configured to select a selectable operation instruction of the plurality of selectable operation instructions to modify the definition of the accelerator.
11 . The computing system of claim 9 , wherein the accelerator comprises a plurality of selectable operation instructions defined for data decompression, wherein the processor is configured to select a selectable operation instruction of the plurality of selectable operation instructions to modify the definition of the accelerator.
12 . The computing system of claim 1 , wherein the coherency agents comprise caching agents, home agents, or both.
13 . The computing system of claim 1 , wherein the processor is configured to coherently read from and write to the memory via the accelerator using the coherency agents.
14 . A memory coherent system, comprising:
a first memory configured to store data;
a programmable logic device coupled to the first memory, wherein the programmable logic device is configured to implement an accelerator to modify the data being stored to the first memory, wherein the accelerator is defined using a hardware description language, wherein the first memory is external to the programmable logic device; and
a processor comprising a second memory, wherein the processor is external to the programmable logic device, and wherein the processor is configured to couple to the programmable logic device that provides access to the first memory for the processor, to process and manipulate the stored data in the first memory by accessing the first memory based on snooping through the accelerator, and to access the first memory and the second memory using coherency agents of a first protocol, wherein the coherency agents are configured to snoop inside the processor and the accelerator and enable the processor to and snoop the first memory using communications through the programmable logic device to provide a coherent interconnection between the first memory and the processor through the programmable logic device, wherein the coherency agents of the first protocol are configured to snoop inside the programmable logic device via second coherency agents of a second protocol, wherein the second coherency agents of the second protocol are configured to coherently interconnect the second memory to the processor, and the processor is configured to modify the accelerator dynamically during a runtime of the memory coherent system based at least in part on the coherency agents being configured to snoop inside the processor and the accelerator.
15 . The memory coherent system of claim 14 , wherein the processor is configured to access the first memory based on receiving instructions of a high-level programming language.
16 . The memory coherent system of claim 14 , wherein the definition of the accelerator is stored in the first memory and the processor is configured to modify the definition of the accelerator by accessing the first memory based at least in part on the coherency agents being configured to snoop inside the processor and the accelerator.
17 . The memory coherent system of claim 14 , wherein the processor is configured to apply a partial reconfiguration to the accelerator during runtime using a coherent interconnection protocol.
18 . The memory coherent system of claim 14 , wherein the coherency agents comprise caching agents, home agents, or both.
19 . The memory coherent system of claim 14 , wherein the first memory comprises a random access memory and the second memory comprises a cache disposed inside the processor.