Data transfer for discrete data

1 . A data processing method, comprising:

determining a source data address and a destination data address of data corresponding to a decoded processing instruction when the decoded processing instruction is a data transfer instruction,

wherein an operation field of the decoded processing instruction includes a source data base address, a destination data base address, a single point data size, a single point data number, an offset vector base address of a single data point, and an offset size,

wherein the source data base address represents current base addresses of a plurality of discrete data points in a data storage space,

wherein the destination data base address represents a base address in the data storage space to which a plurality of pieces of data are to be transferred,

wherein the source data address and the destination data address are located in the same data storage space,

wherein the single point data size represents a data size of each of the plurality of discrete data points,

wherein the single point data number represents a count of the plurality of discrete data points,

wherein the offset vector base address of the single data point represents an offset base address of each of the plurality of discrete data points relative to the source data base address, and

wherein the offset size represents a width of an offset address corresponding to each of the plurality of discrete data points, and the offset size is equal to the single point data size;

obtaining vector data by storing data read from the source data address to the destination data address, wherein the source data address includes a plurality of discrete data addresses, and the destination data address includes continuous data addresses; and

processing the obtained vector data according to a data computation instruction, wherein the data computation instruction includes one of:

performing at least one arithmetic operation, on at least two pieces of the obtained vector data, wherein the at least one arithmetic operation is selected from the group consisting of addition, subtraction, multiplication, and division; or

a difference computation between two pieces of the obtained vector data.

2 . The method of claim 1 , wherein the determining of the source data address and the destination data address of the data corresponding to the decoded processing instruction when the decoded processing instruction is the data transfer instruction includes:

determining source data addresses of the plurality of pieces of data respectively according to source data base addresses and data offset addresses of the plurality of pieces of data in an operation field of the decoded processing instruction.

3 . The method of claim 1 , wherein the determining of the source data address and the destination data address of the data corresponding to the decoded processing instruction when the decoded processing instruction is the data transfer instruction includes:

determining destination data addresses of the plurality of pieces of data respectively according to destination data base addresses and data sizes of the plurality of pieces of data in an operation field of the decoded processing instruction.

4 . The method of claim 1 , wherein the obtaining of the vector data by the storing of the data read from the source data address to the destination data address includes:

reading each piece of data from the source data address of each of the plurality of pieces of data respectively; and

obtaining the vector data by storing each of the plurality of pieces of data to the destination data address sequentially.

5 . The method of claim 1 , further comprising:

obtaining the decoded processing instruction by decoding a received processing instruction, wherein

the decoded processing instruction contains an operation code, and

the operation code is used to indicate performing data transfer processing.

6 . A data processing device, comprising:

an address determining circuit configured to determine a source data address and a destination data address of data corresponding to a decoded processing instruction when the decoded processing instruction is a data transfer instruction,

wherein an operation field of the decoded processing instruction includes a source data base address, a destination data base address, a single point data size, a single point data number, an offset vector base address of a single data point, and an offset size,

wherein the source data base address represents current base addresses of a plurality of discrete data points in a data storage space,

wherein the destination data base address represents a base address in the data storage space to which a plurality of pieces of data are to be transferred,

wherein the source data address and the destination data address are located in the same data storage space,

wherein the single point data size represents a data size of each of the plurality of discrete data points,

wherein the single point data number represents a count of the plurality of discrete data points,

wherein the offset vector base address of the single data point represents an offset base address of each of the plurality of discrete data points relative to the source data base address, and

wherein the offset size represents a width of an offset address corresponding to each of the plurality of discrete data points, and the offset size is equal to the single point data size;

a data storage circuit configured to obtain vector data by storing data read from the source data address to the destination data address, wherein the source data address comprises a plurality of discrete data addresses, and the destination data address comprises continuous data addresses; and

a processing circuit configured to process a data computation instruction, wherein the data computation instruction includes one of:

performing at least one arithmetic operation, on at least two pieces of the obtained vector data, wherein the at least one arithmetic operation is selected from the group consisting of addition, subtraction, multiplication, and division; or

a difference computation between two pieces of the obtained vector data.

7 . The device of claim 6 , wherein the address determining circuit includes:

a source address determining sub-circuit configured to determine source data addresses of the plurality of pieces of data respectively according to source data base addresses and data offset addresses of the plurality of pieces of data in an operation field of the decoded processing instruction.

8 . The device of claim 6 , wherein the address determining circuit includes:

a destination address determining sub-circuit configured to determine destination data addresses of the plurality of pieces of data according to destination data base addresses and data sizes of the plurality of pieces of data in an operation field of the decoded processing instruction.

9 . The device of claim 6 , wherein the data storage circuit includes:

a reading sub-circuit configured to read each piece of data from the source data address of each of the plurality of pieces of data respectively; and

a storage sub-circuit configured to obtain the vector data by storing each of the plurality of pieces of data to the destination data address sequentially.

10 . The device of claim 6 , further comprising:

a decoding circuit configured to obtain the decoded processing instruction by decoding a received processing instruction, wherein

the decoded processing instruction contains an operation code, and

the operation code is used to indicate performing data transfer processing.

11 . An electronic device, comprising an artificial intelligence chip that includes a data processing device, comprising:

an address determining circuit configured to determine a source data address and a destination data address of data corresponding to a decoded processing instruction when the decoded processing instruction is a data transfer instruction,

wherein an operation field of the decoded processing instruction includes a source data base address, a destination data base address, a single point data size, a single point data number, an offset vector base address of a single data point, and an offset size,

wherein the source data base address represents current base addresses of a plurality of discrete data points in a data storage space,

wherein the destination data base address represents a base address in the data storage space to which a plurality of pieces of data are to be transferred,

wherein the source data address and the destination data address are located in the same data storage space,

wherein the single point data size represents a data size of each of the plurality of discrete data points,

wherein the single point data number represents a count of the plurality of discrete data points,

wherein the offset vector base address of the single data point represents an offset base address of each of the plurality of discrete data points relative to the source data base address, and

wherein the offset size represents a width of an offset address corresponding to each of the plurality of discrete data points, and the offset size is equal to the single point data size;

a data storage circuit configured to obtain vector data by storing data read from the source data address to the destination data address, wherein the source data address comprises a plurality of discrete data addresses, and the destination data address comprises continuous data addresses; and

a processing circuit configured to process a data computation instruction, wherein the data computation instruction includes one of:

performing at least one arithmetic operation, on at least two pieces of the obtained vector data, wherein the at least one arithmetic operation is selected from the group consisting of addition, subtraction, multiplication, and division; or

a difference computation between two pieces of the obtained vector data.