Voting scheme in a memory page
A system for providing a voting scheme in a memory page is disclosed. The system receives a request from a host device for data. The system identifies a memory page of a memory array of a memory device storing data bits corresponding to the requested data. The data bits are transferred from memory cells of the memory page to sense amplifiers to sense the values of the data bits. Inversion bits for the row address(es) of the memory page are transferred to a voting circuit to conduct a vote using the inversion bits. If the vote indicates that the data bits are inverted, the system flips the data bits prior to providing the data bits to the host device. If the vote indicates that the data bits are not inverted, the system provide the data bits to the host device without flipping the data bits.
1 . A system, comprising:
a host device;
a memory array comprising a plurality of memory cells configured to store a plurality of data bits and a plurality of inversion bits, wherein each inversion bit is associated with a respective row and indicates whether corresponding data bits of the plurality of data bits in the respective row are stored in an inverted state; and
a controller communicatively linked to the memory array, wherein the controller is configured to:
receive, from the host device, a request to read data stored in the memory array;
determine, based on a row address and a column address specified in the request, a memory page of the memory array storing the data;
cause, by at least one sense amplifier, sensing of inversion bits of the plurality of inversion bits for row addresses of the memory page of the memory array;
read the sensed inversion bits and provide the sensed inversion bits to a voting circuit;
determine, via the voting circuit, whether a majority of the inversion bits indicate that the data bits are stored in an inverted state;
flip, in response to the majority of the inversion bits indicating that the data bits are stored in the inverted state, the data bits to generate flipped data bits; and
provide the flipped data bits to the host device.
2 . The system of claim 1 , wherein the controller is further configured to determine that the majority of the inversion bits indicate that the data bits are not stored in the inverted state.
3 . The system of claim 2 , wherein the controller is further configured to provide the data bits to the host device without conducting a flipping operation on the data bits if the majority of the inversion bits indicate that the data bits are not stored in the inverted state.
4 . The system of claim 1 , wherein the controller is further configured to close the memory page after providing the flipped data bits to the host device.
5 . The system of claim 1 , wherein the controller is further configured to activate the memory page after determination of the memory page based on the row address and the column address specified in the request.
6 . The system of claim 1 , wherein the controller is further configured to transfer the data bits from the at least one data sense amplifier to a multiplexer configured to select a portion of the data bits for providing in response to the request.
7 . The system of claim 6 , wherein the controller is further configured to transfer the data bits from the multiplexer to XOR logic circuitry to flip the data bits.
8 . The system of claim 1 , wherein the controller is further configured to transfer the inversion bits associated with the row addresses the memory page to a corresponding inversion sense amplifier prior to transferring the inversion bits to the voting circuit.
9 . The system of claim 1 , wherein the controller is further configured to maintain storage of the inversion bits in the memory array.
10 . The system of claim 1 , wherein the controller is further configured to provide the inversion bits to the voting circuit without transferring the inversion bits for each row address to a multiplexer.
11 . The system of claim 1 , wherein the controller is further configured to repair the data bits using redundant bits prior to flipping the data bits.
12 . The system of claim 1 , wherein the controller is further configured to determine whether the data bits have been corrupted by utilizing at least one error correction bit.
13 . The system of claim 1 , wherein the controller is further configured to provide the flipped data bits to a global data line prior to providing the flipped data bits to the host device.
14 . A method, comprising:
receiving, at a memory device, a request from a host device for data stored in a memory array of the memory device, wherein the memory array is configured to store a plurality of data bits and a plurality of inversion bits, wherein each inversion bit is associated with a respective row and indicates whether corresponding data bits of the plurality of data bits in the respective row are stored in an inverted state;
identifying, in response to the request, a memory page of the memory array storing the data;
causing, by at least one sense amplifier, sensing of inversion bits of the plurality of inversion bits for row addresses of the memory page of the memory array;
transferring the inversion bits sensed for the row addresses to a voting circuit;
determining, via the voting circuit, whether a majority of the inversion bits indicate that the data bits are not stored in an inverted state; and
providing, in response to determining that the majority of the inversion bits indicate that the data bits are not stored in the inverted state, the data bits to the host device without flipping the data bits.
15 . The method of claim 14 , further comprising determining that the majority of the inversion bits indicate that the data bits of the memory page are stored in the inverted state.
16 . The method of claim 15 , further comprising flipping the data bits prior to providing the data bits based on the determination that the majority of the inversion bits indicate that the data bits are stored in the inverted state.
17 . The method of claim 14 , further comprising directly routing the inversion bits to the voting circuit without passing the inversion bits to a multiplexer.
18 . The method of claim 14 , further comprising setting the inversion bits.
19 . A memory device, comprising:
a controller configured to:
determine, based on a request for data, that a memory page of a memory array of the memory device stores data bits associated with the data and a plurality of inversion bits, wherein each inversion bit of the plurality of inversion bits is associated with a respective row and indicates whether corresponding data bits of the plurality of data bits in the respective row are stored in an inverted state;
cause, by at least one sense amplifier, sensing of inversion bits of the plurality of inversion bits for row addresses of the memory page of the memory array;
transfer, to a voting circuit, inversion bits sensed for the row addresses of the memory page;
conduct, via the voting circuit, a vote using the inversion bits to determine whether a majority of the inversion bits indicate that the data bits are stored in an inverted state;
in response to a determination that the vote indicates that the data bits are in an inverted state:
flip the data bits to generate flipped data bits; and
provide the flipped data bits in response to the request; and
in response to a determination that the vote indicates that the data bits are not in the inverted state:
provide the data bits in response to the request.
20 . The memory device of claim 19 , wherein the controller is further configured to perform error correction, redundancy repair, or a combination thereof, prior to flipping the data bits to generate the flipped data bits.